High-Performance Network-on-Chip Architecture with Congestion-Aware Adaptive Routing for Heterogeneous Multi-Core VLSI Systems

Abstract

Due to the high-speed integration of heterogeneous processing elements in modern multi-core VLSI systems, increment in complexity of communication on chip has resulted in acute scalability limits and dynamic congestion in traditional Network-on-Chip (NoC) designs. Deterministic routing schemes although simple and simple to implement cannot scale to non-uniform and bursty traffic patterns that occur with heterogeneous workloads leading to high latency and early network congestion. In order to overcome these shortcomings, this paper presents a high- performance Network-on-Chip architecture with a lightweight congestion-sensitive adaptive routing scheme. This router is proposed to monitor dynamically the occupancy of buffers and the use of links to calculate an actual index of congestion in order to select the paths intelligently without any deadlock. It is designed to make use of optimal hardware overhead and to be able to scale to mesh-based heterogeneous multi-core platforms. Cycle-accurate simulation was done on 4x4 and 8x8 mesh topology with uniform traffic, hotspot traffic, and transpose traffic. Experimental outcomes prove up to 28 percent decrease in typical packet internship and 22 percent raise in saturation throughput and 17 percent increase in energy effectiveness than the traditional XY and partly adaptable routing plans. Hardware synthesis with the help of 45 nm CMOS standard-cell library proves that the proposed congestion-awareness logic imposes less than 6% area overhead with insignificant effects about the critical path delay. These findings confirm the usefulness of the proposed architecture in heterogeneous VLSI systems of high scalability and high performance.