Journal of Integrated VLSI, Embedded and Computing Technologies
Aim: The Journal of Integrated VLSI, Embedded and Computing Technologies (JIVCT),ISSN - 3049-1312 published by the Society for Communication and Computer Technologies (SCCTS), aims to be a leading international platform for disseminating high-quality, peer-reviewed research and review articles in the fields of VLSI (Very Large Scale Integration), embedded systems, and computing technologies. The journal's mission is to advance knowledge, foster innovation, and facilitate practical applications in these interconnected domains, promoting collaboration among researchers, engineers, and practitioners worldwide. Scope: The Journal of Integrated VLSI, Embedded and Computing Technologies (JIVCT), published by the Society for Communication and Computer Technologies (SCCTS), focuses on publishing high-quality, peer-reviewed articles in the following areas: VLSI Design and Architecture: Digital and analog design, FPGA, ASIC, low-power and high-performance circuits, CAD tools. Emerging VLSI Technologies: Nanotechnology, quantum VLSI, MEMS/NEMS, 3D ICs, photonic systems. Embedded Systems: Hardware-software co-design, real-time operating systems, IoT, energy-efficient systems. Computing Technologies: High-performance computing, parallel and distributed systems, cloud and edge computing, AI hardware. System Integration and Testing: SoC and SiP solutions, hardware-software integration, verification, reliability, thermal management. Interdisciplinary Applications: Biomedical systems, automotive electronics, cyber-physical systems, smart sensors, sustainable technologies. Key Features: High-Quality Content: Rigorous peer-review process. Open Access: Freely accessible to a global audience. Interdisciplinary Focus: Encourages integration across various fields. Innovative Research: Highlights novel methodologies and cutting-edge technologies. JIVCT aims to advance knowledge and foster innovation in VLSI, embedded systems, and computing technologies, contributing to advancements in both academia and industry Frequency of publication - It has Three issue per year Language - English Subject - Engineering Year of Starting - 2024 format of publication - Online Only ISSN - 3049-1312
Society for Communication and Computer Technologies
On-Chip Co-Processing Architectures for Concurrent Neuroelectrical and Hemodynamic Signal Analysis
The multimodal brain monitoring systems are progressively combining function of neuroelectrical signals, including electroencephalography (EEG), with hemodynamic signals, including functional near-infrared spectroscopy (fNIRS), to provide both the time-varying and metabolic definition of neural activity. Most current multimodal platforms are based on either off-chip computation or sequential signal processing pipelines, with the result that these platforms exhibit higher latency, power consumption, and do not work well in embedded and wearable applications. In this paper, an on-chip co-processing architecture will be described, designed to provide the capability to analyse both neuroelectrical and hemodynamic signals on the same embedded platform. The design proposed uses processing pipelines that are modality specific and work in parallel with the help of shared memory resource and synchronisation control logic to guarantee time alignment between modalities. Certain design decisions of hardware-based nature such as pipelined data processing, fixed-point calculation, and selective resource utilization are used to accomplish real-time functionality with low area and energy cost. An FPGA-based prototype was used to test the architecture and give it a feasibility evaluation. Experimental evidence indicates that there is an important decrease on end-to-end processing delay in relation to a sequential multimodal baseline, processing efficiency and energy per processed sample is also enhanced. These findings confirm the usefulness of on-chip parallel processing of multimodal neuro-monitoring loads. The suggested architecture offers scalable and energy-efficient real-time embedded brain monitoring and is an ideal solution to the next generation wearable neurotechnology and edge-based brain -computer interface systems.
On-chip processing, co-processing architecture, neuroelectrical signals, hemodynamic signals, multimodal biosignals, embedded systems, VLSI design
Embedded and Cloud Computing Integration for Smart Mobile Learning Applications Using Deep Reinforcement Learning
Smart mobile learning applications are becoming increasingly dependent on embedded devices which run with harsh limitations with regards to computation power, energy, and network variability. Although cloud computing is capable of providing scalable processing, storage capacities, the integration of embedded platforms to cloud infrastructure is still a big problem especially when it comes to use in resource and intensive and latency-sensitive learning applications. In this paper, the author proposes a smart embedded-cloud computing system of smart mobile learning applications relying on Deep Reinforcement Learning (DRL). This proposed solution defines the computation offloading problem and resource allocation issue as a sequential decision-making problem, according to which the DRL agent is a dynamic, in charge of deciding whether the learning tasks need to be performed locally on the embedded system or offloaded through edge servers or cloud servers. State space is a combination of device status, network status and task properties and the reward mechanism serves to manage the combination of execution latency, energy use and quality of service. Numerous experiments performed in a simulated mobile learning setting prove that the suggested DRL-based mechanism is more favourable, compared to traditional local execution, offloading to the cloud, and heuristic-based approaches, in terms of lower latency and energy consumption. The findings demonstrate the scalability and flexibility of DRA on dynamic mobile systems, so that the suggested model is a prospective indicator to the future-generation smart mobile learning systems combining embedded and cloud computing technologies.
Embedded systems; Deep reinforcement learning; Cloud–edge computing; Smart mobile learning; Computation offloading; Energy efficiency
Embedded AI Framework for Low-Latency Sentiment Analysis in Smart Content Curation Systems
The fast spread of digital content on multiple networks has caused the growth of the need of real time sentiment-informed analytics to improve user involvement and content delivery techniques. Convincing cloud-based AI Natural language processing (NLP) solutions, as powerful as they are, typically have a disadvantage in latency, bandwidth consumption and data privacy, in bandwidth-sensitive and low-latency settings. To overcome such issues, the framework of a new embedded artificial intelligence (AI) is provided in this paper to handle low-latency sentiment analysis in intelligent content curation systems. The suggested framework uses quantized deep learning networks that are particularly trained to run on resource-constrained edge computing platforms, i.e., the NVIDIA Jetson Nano and the Raspberry Pi 5. The use of a blend of hardware-aware pruning, 8-bit quantization, and mixed-precision training methods by the framework leads to a large scale of reductions in model complexity, power consumption without leading to predictive accuracy decrease. As experimentally shown, the optimised model has a high classification of 92 percent on a benchmark sentiment dataset and a reduction inference latency of less than 150 milliseconds, which is much lower than the limit of the real-time processing. In addition to that, power consumption is also minimised by 34 percent against baseline full-precision models, which underscores appropriateness of the strategy to embedded application with energy-saving. The system architecture integrates an effective data acquisition system and light weight text preprocessing platform and a real time inference system, which allows the smooth integration into intelligent media applications. This paper creates a base of the forthcoming embedded NLP systems, those able to work autonomously and effectively in semi-autonomic settings. It also highlights the possibility of using affordable hardware to do more intricate AI work and, in general, expand accessibility and scalability to real-life applications. These findings make this framework a practical option towards real-time sentiment analysis in intelligent communication infrastructure, personalised recommendation systems, as well as adaptive media content moderation in mobile and embedded systems.
Embedded AI, edge computing, deep learning optimization, low-latency inference, quantization, smart content systems
Embedded Machine Learning Framework for Real-Time Prediction of User Information Needs in Intelligent Systems
Embedded computing combined with machine learning has offered new opportunities of intelligent and context-aware systems able to make real-time decisions at the network edge. The paper presents a lightweight embedded machine learning system that can be used to make predictions on the information required by users dynamically in smart information retrieval scenarios. The suggested architecture incorporates enhanced neural designs into a Raspberry Pi 5-based edge device, making it be locally assertive to a cloud connexion. The system consists of a predictive core that is a compressed and quantised neural network, which has been trained with anonymised data of user interaction and search behaviour. The systematic optimization to 93 % prediction accuracy, 200 ms mean inference latency, and under 5 W power consumption allows real-time user intent prediction to be successfully run on the resource constrained hardware, which offers a basis to privacy preserving, low latency intelligent systems. It proves that it is practically feasible to introduce adaptive learning directly into edge devices, opening the way to the next generation of cognitive interfaces in which seamless interaction between perceptions, reasoning and individual user support is built into practical application.
Embedded systems, machine learning, edge computing, real-time analytics, neural inference, information retrieval, intelligent systems.
Embedded System Architectures for Passive IoT Device Monitoring
In this paper, a new embedded system architecture that is used to passively monitor and classify Internet of Things (IoT) devices behavior on the edge layer is introduced. The study will help fulfil the requirement of real time and non-invasive analytics in distributed smart settings where bandwidth, power, and computational resources are constrained. Visions of the proposed design The design is a unified co-design of the hardware and software based on an ARM Cortex-A processor and a reconfigurable FPGA-based packet capture engine. The high-speed data acquisition and timestamping is performed by the FPGA logic, whereas lightweight behavioral analytics and classification is performed by the ARM core. Observing metadata (passively) of communication allows profiling devices continuously without disrupting network protocols or causing extra latency. Results of experiments carried out on several embedded IoT testbeds show that it has an average detection latency of less than 3 ms and overall power consumption of only 2.8 W with continuous operation. Comparative measurements show higher adaptability and more precise measurement compared to the static and monitored baselines, and this proves that the suggested architecture is viable when it comes to edge-oriented behavioral monitoring. The results indicate that passive embedded architectures may contribute immensely to improving IoT visibility and trust assurance and still remain scalable and energy efficient in scale and large, heterogeneous deployments.
Embedded systems, IoT monitoring, FPGA, passive data capture, edge analytics, low-power design.
Hardware Acceleration of SSL/TLS Handshake Operations Using Embedded Cryptographic Engines
The handshake of the SSL/TLS in the times of ubiquitous connectivity and services based on data is a basic but computationally expensive part of safe communication. In this paper, a hardware-assisted variant of the SSL/TLS handshake accelerator is proposed and implemented in embedded and edge devices, with cryptographic operation optimization by use of modular cryptographic engines, implemented in FPGA. Its architecture can use RSA, ECC and AES-GCM algorithms and can easily integrate with tight embedded spaces. With the proposed system, the handshake completion time is improved 3.2-fold and the CPU usage has been reduced by 45 % in comparison to the traditional software-only systems due to the offloading of the compute-intensive encryption and decryption operations to a custom hardware module. The modular structure of the accelerator enables flexibility to work on any edge computing and IoT environment. Through experimental validation, real-time encryption offloading is feasible and that it enhances throughput by a large margin and latency is minimized to support secure IoT and web applications. In this study, the research paper highlights the possibility and practicality of cryptographic acceleration using a hardware-based approach as a foundation of next-generation low-latency secure communications models.
SSL/TLS accelerator, FPGA, embedded systems, cryptographic engine, handshake optimization, hardware offloading, latency reduction
Ultra-Low-Power VLSI-Enabled Embedded Systems for Neural Prosthetics: Toward Scalable and Real-Time Brain–Machine Interfaces
BMIs and neural prosthetics bring a world-revolutionizing promise in terms of defeating sensory and motor impairments in patients with neurological deficiencies. The current systems have severe drawbacks usually in the aspects of energy efficiency, effective interfacing with hardwares, and real-time capability, which renders them inappropriate in several wearable or implantable applications over a long period. The given paper suggests an ultra-low-power embedded architecture based on VLSI that has been especially tailored to overcome such limitations and facilitates elastic resource-constrained neural signal processing in real-time. The main aim of this study is to develop the compact, energy-efficient system-on-chip (SoC) platform which will consist of neural signal acquisition, spikes-based preprocessing, and embedded classification consumption of minimum power. The system is equipped with subthreshold analog front-end, hardware-efficient spike detectors, and a lightweight, embedded neural decoder combined with a dynamic power management unit, to reduce the energy requirements according to the demand of the workload. Simulation and FPGA-based prototype show that the system is capable of processing up to 64 channel of neural traffic at a rate exceeding 300 000 channels/second with average power-consumption below 120 micro-watts/ channel and a total processing-latency of 2.8 milliseconds. A comparative study shows major reduction in the amount of power consumption (~70%) compared to existing designs, without killing the signal fidelity or the decoder accuracy. This shows the functionality of the offered architecture and makes it appropriate to be implemented in next-gen neural prosthetic systems.In summary, the candidate VLSI-based embedded system offers a good way of creating ultra-low-power, real-time brain machine interfacing that can perhaps be used in an implantable biomedical device, adaptive neuro prosthesis, and closed loop neural control machine.
VLSI Architecture; Neural Prosthetics; Ultra-Low-Power Embedded Systems; Brain–Machine Interface; Real-Time Signal Processing; Subthreshold Circuits; Dynamic Power Management
Thermal-Aware Floorplanning and Optimization Framework for High-Performance Heterogeneous SoC Architectures in Edge-AI and Embedded Systems
The extreme growth of edge-AI and embedded systems has made it necessary to incorporate a range of dissimilar computing assets, such as CPUs, GPUs, NPUs, and memory blocks, into the same system-on-chip (SoC). The trend towards this kind of architecture ushers in extreme thermal management issues that affect reliability, performance and power efficiency. In this paper, a floor planning and optimization algorithm that is thermal conscious is proposed especially in high-performance heterogeneous SoC architecture. The potential framework has low peak temperature, reduces the thermal gradient, has more reliability of the entire system in that it is a combination of early stage thermal modelling, power density conscious placement algorithm, and dynamic thermal challenge approval. With simulation of real-world edge-AI workloads, up to 28 per cent fewer thermal hotspots and a 17 per cent better thermal uniformity were measured compared to commonly used floorplanning approaches. This paper is pioneering towards scalable thermal-driven design behaviors of embedded AI SoCs in future generation.
Thermal-aware floorplanning, Heterogeneous SoC, edge computing, AI accelerators, thermal modeling, floorplanning optimization, thermal hotspots, reliability, embedded systems, chiplet integration.
Carbon Nanotube FET-Enabled VLSI Architecture for Energy-Efficient Deep Learning Accelerators in Edge AI Systems
The growing need to apply edge artificial intelligence (AI), including technologies like live image recognition, self-driving cars and healthcare logistics, requires both energy-saving and high throughput hardware solutions. Conventional power-hungry CMOS-based accelerators are significantly affected by power, scaling, and thermal constraints, which encourages the development of exploratory approaches to new device technologies. The proposed VLSI architecture in this study is a Carbon Nanotube Field-Effect Transistors (CNTFETs) based deep learning accelerator, due to its outstanding electrical characteristics, such as ultra-high carrier mobility, extremely low leakage current, and great scalability. The aim is to design and prove the effectiveness of a convolutional neural network (CNN)-optimised CNTFET-optimised architecture to fit resource-constrained edge computing conditions. As energy consumption is a concern in the proposed system it uses quantization at arithmetic operators, memory-efficient dataflow, and power-gates on memory banks. The 7 layer CNN was implemented and simulated at both architecture and CNTFET device-level behaviors at 7-layer with Verilog (architecture level) and HSPICE (device level for CNTFET devices). The findings illustrate a 53 percent better energy usage and 41 percent less silicon extent than corresponding CMOS-based plans with little performance reduction. The results demonstrate the promise of CNTFET-based designs and architectures as potential future energy-efficient edge artificial intelligence hardware, in the emerging neuromorphic computing and deep learning fields.
Carbon Nanotube FET (CNTFET), VLSI Architecture, Deep Learning Accelerator, Edge AI Systems, Energy Efficiency, Quantized Neural Networks, Hardware Accelerator, Low-Power Design
Bio-Inspired Computing Architectures for Energy-Efficient Biomedical Signal Processing on Chip
Real-time biomedical signal processing has used a lot of energy-efficient applications, and with the increasing number of wearable, implantable, and portable healthcare instruments, the necessity will increase. The traditional von Neumann-based architectures provide high flexibility but with memory bottleneck and power consumption they are inapplicable in continuous monitoring anomalies in resource-constrained systems. In that regard, a new solution can be considered in bio-inspired computing architectures that reproduce the general features of the parallel, event-based, and low-power human brain. In this paper we present a neuromorphic computing architecture of the biomedical signal processing on-chip by spiking neural networks (SNNs) and analog-digital mixed-signal integrations. The architecture consists of an analog front-end consuming very low power to perform real-time acquisition of biosignals and coding of the spikes, and a digital SNN core to perform the sparse and asynchronous processing. The system was designed and simulated using a 65nm CMOS technology that makes it very energy efficient and latency efficient. In particular, it can realize up to 65 percent of energy savings per inference count and up to 40 percent low-latency processing over traditional biomedical processors using DSPs. It is tested with benchmark biosignal data such as ECG (MIT-BIH), EEG (Bonn university), and EMG (Ninapro) with use cases such as arrhythmia detection, epileptic seizure prediction, and gesture recognition that can be utilized in the prosthesis control. They include on-chip learning and high noise resistance of the spike-based representation and adaptive SNN classification, which makes the overall architecture more reliable in the environment where it would be used in practice in the biomedical setting. Due to the vast simulation efforts and comparison studies, the suggested structure shows a great possibility of providing a feasible architecture to the next-generation edge medical devices which requires ultra-low-power and real-time. The fact that it is reconfigurable and can be compatible with contemporary CMOS processes opens up the possibility of scalable applications of the same on a broad range of biomedical monitoring systems. The contribution of this work is the progress of neuromorphic engineering in the field of healthcare, where the biological efficiency and low power consumption found in nature are achieved and enter the device silicon domain in which personalized and continuous health monitoring can be delivered.
Bio-Inspired Computing, Neuromorphic Architecture, Spiking Neural Networks, Biomedical Signal Processing, Energy Efficiency, Edge AI, On-Chip Learning, Low-Power VLSI
Photonic VLSI Architectures for Ultra-Low-Latency High-Speed Signal Processing in 6G Edge Networks
The demand-driven by next-generation wireless networks has caused exponential growth in the number of applications that use data and the latency and throughput of data processing at an edge scale. Although traditional electronic Very-Large-Scale Integration (VLSI) designs have been well developed, they face fundamental challenges in terms of speed, bandwidth scalability, and energy efficiency skills, mainly in the polarizing performance demands of 6G edge environments. The paper offers the fresh idea of a photonic VLSI that incorporates the silicon photonics into a traditional VLSI structure to address these bottlenecks. It is proposed that the photonic-based interconnects, logic gates implemented in MachZehnder interferometer (MZI), and wavelength-division multiplexing (WDM) will be used in the proposed architecture to provide parallel high-bandwidth optical transmission of data and parallel computation of signals at ultra-fast speed. We describe a modular systems-based optics design flow and thoroughly simulate-based benchmark with the state of the art CMOS systems. Our findings prove that the architecture can operate up to 62 per cent faster in terms of latency, 5.2 times faster in terms of content delivery performance and corresponding low values of energy-per-bit, which proves the applicability of the approach in real-time signal processing in 6G edge networks. The overall learning point of the study is that photonic VLSI systems provide a scalable and energy-efficient avenue to address the excessive requirements of terabit-scale edge intelligence in subsequent 6G systems and establish the foundation of the future hybrid optoelectronic compute architecture.
Photonic VLSI, 6G Edge Networks, Ultra-Low-Latency, High-Speed Signal Processing, Silicon Photonics, Wavelength-Division Multiplexing (WDM), Optical Interconnects, Mach-Zehnder Interferometer (MZI), Edge Computing, Energy-Efficient Architectures, Optical Logic Gates, Electro-Optical Interfaces, Next-Generation VLSI, Terabit-Scale Data Processing, Real-Time Communication Systems
Design and Implementation of a Low-Power RISC-V Processor Core for Energy-Constrained Edge Devices
The paper entails the entire design and implementation of the energy efficient low power RISC-V processor core tailored specifically to energy limited edge computing platforms including wireless sensor networks, wearable biomedical device and intelligent IoT end points. As edge devices scale exponentially and demand efficient computing capability on-device, there is an urgent demand of programming frameworks which achieve custom and ultra-low power processing architectures to perform well within limited-energy constraints. The proposed processor core uses the open-source, modular design of the RISC-V instruction set architecture (ISA) to implement powerful low-power design techniques such as fine-grain clock-gating, power-gating and instruction-level parallelism to minimize dynamic and steady power usage. A five-stage pipeline based architecture that implements without some, or with some compressed instructions (RV32C), the RV32IM instruction set architecture has been implemented with System Verilog and has been prototyped and tested with a low-power FPGA development board. Application-specific benchmarks of real world IoT workloads have provided guidance on power-aware design decisions made in designing processors in IoT applications, including: sensor data processing, lightweight cryptography, and control logic calculations. Experimental analyses indicate that the suggested RISC-V essence attains an energy efficiency advantage of up to 43 percent over conventional RISC-V characters, with a similar computing performance and an insignificant area cost. Also, the design proves compatible with DVFS (Dynamic Voltage and Frequency Scaling) based methods which makes it even more appropriate to be used in energy-harvesting and battery-powered applications. All the processors are benchmarked with Vivado and ModelSim and power analysis with Vivado Power Estimator, and Synopsys PrimePower. The findings show that switching activity and leakage power has been reduced drastically in all test conditions. The work contributes to a feasible reference architecture that may be adopted by researchers and practitioners to design energy-autonomous embedded applications and systems, as well as the larger scope of scaling, and sustainability of edge intelligence in the next-generation ubiquitous computing systems. The next improvements will incorporate the use of ASIC implementation and collaboration with domain-specific accelerators of AI-powered tasks at the edge.
RISC-V, Low-Power Processor, Edge Computing, FPGA, IoT, Energy Efficiency, Clock Gating, Power Gating.
Hardware–Software Co-Design of RISC-V Embedded Systems for Ultra-Low-Power IoT Applications
This study intends to solve this challenge by suggesting a hardware-software co-design framework of ultra-low-power embedded systems using the RISC-V open-source architecture. The resulting system goes to extremes to maximize the hardware and software abstractions to satisfy problem-specific energy requirements, all the whilst maintaining efficiency of performance and scalability. The methodology offered consists of customization of instruction sets, hardware-based clock and power gating, and low-level software based technique inside compiler based optimization, sensor-sensitive task scheduling, and memory access improvement. An iterative profiling and tuning of a system can be done in a co-simulation system based on Verilator and Spike. A RISC-V core incurs environmental sensor workloads to validate the experimentally. Design All the co-designers showed an average power consumption of 38% (versus conventional ARM Cortex-M4 baseline), a 46 percent energy efficiency gain per task. Dynamic voltage and frequency scaling (DVFS) is another feature that can support flexibility of varying workloads. The conclusion of this research is that the hardware-software co-design applying RISC-V provides a suitable, extensible, open, and energy-efficient approach to the following-generation IoT devices. It is specially tailored to battery-powered and energy-gathering embedded platforms that can be later applied into the real deployment across smart environments, health, and industrial monitoring.
RISC-V, hardware–software co-design, ultra-low power, embedded systems, IoT, instruction set customization, power optimization, edge computing
3D IC Integration with Through-Silicon Vias for High-Density Computing Applications: Design and Thermal Considerations
The 3D integrated circuits (3D ICs) enabled by the technology of Through-Silicon via (TSV) has become a transformative technology to high density-computing application that overcomes the limitations of the traditional planar IC architecture, including the additional interconnect delay, interconnect bandwidth bottlenecks, and huge footprint. The ability of 3D ICs to allow vertical stacks of logic, memory, and compute layers allows greater performance, lower latency, and enormous area benefits. The application of many active layers, however, adds much design, temperature management complexity, especially relating to power density, thermal dissipation, and TSV-related stress. In reviewing this paper, you shall see that significant research has been conducted with regard to the design style, fabrication techniques as well as thermal factors linked to TSV-based 3D ICs. It describes such architectural strategies as floor planning, optimization of interconnects, and co-design of power delivery as well as advanced TSV fabrication processes such as deep reactive ion etching (DRIE) and copper electroplating. Thermal modeling in finite element analysis, simulation-based thermal hotspot evaluation with and without mitigation approaches such as thermal TSVs, and microfluidic cooling are given special attention. The example of a 3-tier AI accelerator stack is presented to illustrate how vertical integration affects performance metrics, showing a 35 percent decrease in latency and 50 percent area savings over 2D devices, as well as pointing at the potential threats of the thermal buildup due to the lack of effective cooling systems. Reliability and application in thermal, profiles and comparative performance analysis are presented to give a full picture of an 3D IC operation in a real-life workload. The paper also ends with the future research directions to be pursued such as TSV-free monolithic 3D ICs, AI-enabled thermal-aware design automation, and electronic-photonic integration. Its results form part of the effort to design thermally robust, performance-optimized 3D IC structures that can deliver on the performance requirements in the next-generation artificial intelligence, edge computing, and high-performance data centers.
3D IC, Through-Silicon via (TSV), Thermal Management, High-Density Computing, AI Accelerator, TSV Fabrication, Vertical Integration, Microfluidic Cooling, Power Delivery Network, Floor planning
Hybrid CMOS-Photonic VLSI Interconnects for Ultra-High Bandwidth and Energy-Proportional Chiplet Communication in 2.5D/3D Systems
The emerging intensive nature of data transfer in artificial intelligence (AI), cloud computing, and high-performance computing (HPC) increased the need to shift towards chiplet based systems. Nevertheless, conventional electrical connecting devices are fast being ill equipped to cater the bandwidth density, energy efficiency and thermal management factors in 2.5D/3D integrated system. With the introduction of CMOS-photonic VLSI systems-on-chip, ultra-high bandwidths and energy-proportional communication within and across chiplets are feasible in advanced packaging environments. This paper determines and proposes a hybrid CMOS-photonic VLSI interconnect architecture, which can achieve those ultra-high bandwidths and energy-proportional communication. To attain this goal, we suggest that a CMOS-compatible silicon photonic architecture be co-designed with electrical SerDes and interface circuitry so as to incorporate CMOS-compatible silicon photonic components, e.g., MachZehnder modulators (MZMs), ring modulators, and photodetectors. The energy management framework of workload-aware is also integrated to adjust power consumption of optical link dynamically according to the traffic demand. The proposed system is simulated as a multi domain system that involves CST Microwave Studio to design the electromagnetic part, COMSOL Multiphysics to model the thermal design and Synopsys OptSim to model the photonic link in the system. Simulation results show up to 10x bandwidth advantage and more than 60 percent energy-per-bit savings of a hybrid architecture over conventional copper based interconnects. Moreover, due to optimized layout design using TSV, the thermal simulations indicate that the proper cooling of the device can be achieved under its peak workloads. In summary, the hybrid CMOS-photonic interconnection proposed is an energy efficient, scalable and thermally feasible communication systems used in chiplets in 2.5D/3D chip fabrication providing solution to the bandwidth and energy bottlenecks of layer-to-layer communication in heterogeneous computing chip systems.
Hybrid CMOS-Photonic Interconnects, 2.5D/3D Integration, Chiplet Communication, Silicon Photonics, Energy-Proportional Design, High-Bandwidth On-Chip Communication, Thermal-Aware Packaging, VLSI System Architecture
Thermal-Aware System-on-Chip (SoC) Design for Real-Time Edge AI in Smart Healthcare Devices
This study aims at contributing to the thermal management issues that would arise when integrating AI features on a System-on-Chip (SoC) platform to perform real-time health monitoring on smart healthcare gadgets. With AI workloads getting more compute-intensive, particularly in wearables and implantable medical devices, the potential thermal limitations present an acute design concern in terms of performance and user safety. The paper suggest a thermal-aware SoC architecture, optimized towards edge-based applications of AI in healthcare. This method uses dynamic voltage and frequency scaling (DVFS), thermal-sensitive task scheduling and predictive throttling algorithms to use thermal sensors and optimize core placement spatially. The system has been made in such a way that full inference will be available in real time and minimize hotspots. The offered system was tested in comparison with the benchmark healthcare AI models (ECG classification and fall detection on a simulated AI-SoC prototype). The results indicate potential peak temperature level decreasing by up to 18 percent, an average inference latency of 58 milliseconds, and the power management overhead of fewer than 6 percent, which make it suitable to be used in medical-grade conditions during continuous monitoring. To summarize, the study has yet presented a scalable, thermally optimized AI-SoC, optimized to support smart healthcare. These results form the foundation of a safer and more reliable edge AI devices that will encourage the long-term implementation of a real-time diagnostics in health-critical facilities.
Thermal-Aware SoC Design, Edge AI Computing, Smart Healthcare Devices, Dynamic Voltage and Frequency Scaling (DVFS), On-Chip Thermal Management, Neural Processing Units (NPUs), Low-Power Medical AI Hardware, Real-Time Inference, Wearable and Implantable Devices, AI-Driven Thermal Optimization.
Reliability Analysis and Hardware Fault Injection for Safety-Critical Embedded Applications
A safety-critical embedded system is central to all applications that cause serious effect in case of failure, such as human injury, financial impact, or disruption of the entire system. Such systems are widely used in the realms of automotive control (e.g., automatic braking), airline navigation, automation of industrial processes and life-support medical devices. Therefore, their reliability and fault-tolerance of operation are a top priority. The proposed work presents a detailed framework of reliability analysis coupled with hardware fault injection (HFI) methodology that brings the serious fault tolerance capabilities of real-world fault scenarios of embedded systems under testability. The suggested approach will unite formal reliability modeling, where such metrics like the failure rate, mean time between failures (MTBF), fault recovery rate (FRR), and the mean time to recovery (MTTR) will be used, and the hardware fault injection based on the experimental hardware application, both FPGA-based platform and microcontroller-based platform. Classes of faults that the study systematically addresses are stuck-at faults, transient faults and memory corruption faults through the processor registers, memory arrays and within I/O peripherals. Two of their benchmark applications: an autonomous braking controller and a ventilator feedback system are safety-critical and made subject to controlled fault injection campaigns. The experimental data in terms of fault recovery prove that the fault recovery ratio is very high 94.7%, the system lacks significant fractional time in the fully down mode, and fast recovery is centralized on possessing redundant architectural elements and error-correcting codes (ECC). In addition, the trade-offs between area/power overheads and fault coverage are analyzed in terms of normal and abnormal detection latencies. The paper does not only prove the efficiency of the suggested fault-tolerant mechanisms, but also identifies certain potential weaknesses in the design that may go unnoticed in the traditional scheme of simulation-based testing. The framework complies with steps of functional safety, including ISO 26262, and IEC 61508, in terms of confirming pre-certification validation and soundness profiling of embedded systems. In general, the research introduces an ingenious scalable hardware-verified methodology of improving the resiliency of safety-critical embedded systems, and furthermore, leads the way to future applications in embedded system design involving the exploitation of smart fault prediction and fault mitigation policies.
Safety-Critical Embedded Systems; Hardware Fault Injection (HFI); Reliability Analysis; Fault Tolerance; Redundant Design; ECC; Safety Standards; Fault Recovery Rate (FRR); FPGA-Based Injection; Real-Time Monitoring; ISO 26262; MTTR.
A Scalable Parallel Processing Architecture for Real-Time and Energy-Efficient Biomedical Signal Analysis in Edge-Enabled Health Monitoring Systems
The trend in wearable Biomedical devices that integrate continuous health monitoring capabilities has also necessitated the need to analyze the wide range of signals in real-time with energy-efficient analysis at the edge. High latency and the lack of scalability require new line-based processing architectures that are more appropriate to perform the real-time computation of electrocardiogram (ECG), electroencephalogram (EEG), and electromyogram (EMG) signals processing. This paper presents a scalable work detector which is tailored towards edge enabled health monitoring systems and which has the goal of parallel processor architecture. The architecture incorporates the modular pipeline architecture and a hardware/software co-design approach such that preprocessing, feature extraction, and classes can be done simultaneously. Versatile balancing of work load across the numerous processing elements promises optimal performance and utilization of energy. It is prototyped on an FPGA based platform with embedded ARM cores and custom accelerators, and it is demonstrated based on real data in the biomedical applications. Results of experimentation show a 65% depletion of the processing latency and 48% enhanced energy efficiency as compared to single-core systems. These results indicate that the proposed architecture can serve as an efficient and scalable architectural solution that can help to realize real-time biomedical signals analysis in future edge-AI healthcare equipment.
Real-Time Signal Processing, Biomedical Signal Analysis, Edge Computing, Scalable Parallel Architecture, Hardware/Software Co-Design, ECG, EEG, EMG, FPGA Implementation, Energy-Efficient Processing, Wearable Health Monitoring
AI-Integrated System-on-Chip (SoC) Architectures for High-Performance Edge Computing: Design Trends and Optimization Challenges
This leads to the fact that the development of edge applications in autonomous systems, healthcare, and smart environments requires very efficient and scalable computing frameworks. The paper gives an overview of the state-of-the-art of AI-integrated System-on-Chip (SoC) architectures being tailor-made to satisfy performance, energy, and latency requirements of the modern edge computing. This is aimed at examining how the embedded AI accelerators (e.g. neural processing units (NPUs) and digital signal processors (DSPs)) may be easily implemented in heterogeneous SoC platform. Methodologically, the research analyzes the progress of the last few years in the field of hardware-software co-design, dataflow and memory hierarchies. It also looks into heterogeneous core coupling plans, thermally conscious floor planning, and energy-conscious task scheduling. Comparative lessons based on commercially available SoCs such as Apple ANE, Google Edge TPU, and NVIDIA Jetson are given in an attempt to highlight trade-offs in the real world. Indicators demonstrate that AI-tailored accelerations--including systolic array-based accelerators, near-memory computing and quantization-aware processing--are representative of multi-seemingly magnified inference acceleration and power efficiency. But the problems encountered are scaling the memory bandwidth, real-time workload scheduling, as well as thermal dissipation. It is observed in conclusion of the paper that the future AI-SoC architectures should focus on being modular, reconfigurable, and secure with runtime and power profiles that allow them to be used at the edge. This overview lays out helpful design considerations and outlines every major research area of projected work on the next-generation SoCs with a means to sustain, intelligent computing at the edge.
AI-SoC Architectures, Edge AI Computing, Neural Processing Units (NPUs), Heterogeneous System-on-Chip, Low-Power Inference, Hardware-Software Co-Design, Embedded AI Accelerators, Thermal-Aware SoC Design, Real-Time AI Processing, Energy-Efficient AI Hardware
Energy-Efficient 3D-Stacked CMOS–Memristor Hybrid Architecture for High-Density Non-Volatile Storage in Edge Computing Systems
In response to these recent augmented demands of the edge computing systems in terms of compact size, low power consumption, and high density non-volatile storage, this paper develops an innovative 3D-stacked CMOS-memristor hybrid structure, which is energy efficient in the application contexts of edge settings. The goal is to surpass the drawbacks of conventional memory technologies, i.e., SRAM and Flash, that face scalability bottlenecks, high leakage, and poor endurance. The proposed new architecture invokes vertical integration of memristive crossbar memory stacked on top of CMOS control and logic layers with the use of through-silicon vias (TSVs), thus allowing exceptionally dense memory packing and opening up the possibility of in-memory computing with a drastic reduction in data transfer energy. Integrating memory and computation into a 3D stack, the architecture lends itself to logic-in-memory functionality and matrix-vector multiplication-the two operations that play a pivotal role in accelerating edge-AI applications with minimal cost in terms of additional energy consumption. The evaluation of the system uses a complete methodology of device-circuit co-simulation, thermal modeling and performance benchmarking. The results show that write energy is reduced by 42 percent, read latency is improved by 28 percent and that it has 3.8 times the storage density of conventional memory systems. Dependability estimation on process deviations and thermo-stress in addition to endurance tests based on computer simulation demonstrate the cycle stability to be far more than 10 11 write. These results indicate that the CMOS memristor hybrid technology promises not only improvements in energy, efficiency, and scalability of memory, but also an effective paradigm of energy-aware near-memory computing, which can make this technology suitable to the next generation edge-AI and Internet of Things (IoT) applications.
3D integration, memristor, CMOS, edge computing, non-volatile memory, hybrid architecture, energy-efficient storage, neuromorphic systems, in-memory computing, high-density memory.
Design and Implementation of a Reconfigurable ASIC Architecture for Low-Power Secure Communication in IoT Devices
The goal of the paper is to introduce and describe low-power and secure reconfigurable ASIC architecture as a solution optimized to operate in resource-constrained Internet-of-Things (IoT) devices. The main aim would be to come up with a new hardware product which intertwines efficient use of energy, lightweight cryptographic processing and dynamic runtime scalability to fit the requirements of the next-generation IoT platforms. The suggested system incorporates a cryptographic engine which is centered on PRESENT cipher, configurable key-length (80/128 bit ), power-saving characteristics like clock gating and power gating. This was proved in 65nm CMOS technology and synthesized on Synopsys Design compiler, and its functional and timing verification was done with the Cadence post layout simulation tools. The architecture meets all the requirements, and experimental results show that the architecture can be used in a battery-powered and wearable IoT, as it has peak throughput of 45 Mbps, a total power consumption of less than 1.5 mW at 0.9 V. It also has minimal area and latency overhead to allow the architecture of enabling adequate runtime reconfiguration between encryption modes. Scalability Single-chip that solves the dilemma of low-power and data confidentiality in the IoT communication ecosystem: The proposed design proposes a scalable and efficient solution to Hardware security. It also provides an already successful base of further development with the inclusion of post-quantum cryptographic support and increased resistance to side-channels.
Reconfigurable ASIC, IoT Security, Low-Power VLSI, PRESENT Cipher, Cryptographic Engine, Hardware Security, Secure Communication, Clock Gating, Power Optimization, CMOS Implementation
Performance Evaluation of CNTFET-Based 6T SRAM Cell for Next-Generation VLSI Circuits
In an attempt to increase the performance of memory within the next generation of VLSI circuits Carbon Nanotube Field-Effect Transistors (CNTFETs) have been of great interest as possible replacements of conventional CMOS transistor devices, due to their high degree of electrostatic integrity, ballistic range of carrier transport, high current drive sensitivity and good scaling performance. The paper proposes the design, modeled and performance analysis of a 6T SRAM (Static Random Access Memory) cell using CNTFET (Carbon Nanotube Field Effect Transistor) at 32nm technology node that deploys the Stanford CNTFET SPICE model to perform realistic device level simulation. The suggested design used the same convention 6-transistor design, but instead of using CMOS components, it uses equivalent CNTFET devices so it remains functionally compatible and it is easy to benchmark the ideas. The most important performance indicators, like static noise margin (SNM), read/write access delay, power dissipation, and resistance to process-voltage-temperature (PVT) variations are thoroughly discussed and compared to that of a typical CMOS 6T SRAM implementation. The simulation results promote that the CNTFET based 6T SRAM configuration has better SNM, lesser dynamic power dissipation, and speedier write performance and hence a strong candidate in high performance, low power embedded memory architectures. In particular, CNTFET SRAM PNM shows ~60x better SNM and as much as 40x lower write power as CMOS, due to superior electrostatic control and tunability of threshold voltage possible in CNTFETs. Moreover, small-scale size and relativistic semiconducting characteristics of CNTFETs make them even more adaptable to customize to suit area and energy efficiency. It is process robust, and read/ write operations are stable over a broad range of both voltages and temperatures. These properties make CNTFET-based SRAM a surrounding application in ultra-dense memory systems of the next-generation computing system (mobile processors, AI accelerators, and low-power SoCs). The study presents a promising outlook of the CNTFET technology and potential of this technology in changing the field of memory-centric VLSI design and makes an appeal towards undertaking more study on the integration of CNTFET technology to circuits and system-level.
CNTFET, 6T SRAM, VLSI, Static Noise Margin, Low-Power Memory, Emerging Nanodevices
Design and development of Two Stage Operational Trans-conductance Amplifier with single ended output for EEG Application
In this work, a two-stage operational transconductance amplifier (OTA) with a single-ended output for electroencephalogram (EEG) applications is designed and developed. Amplification of biomedical signals, such EEG, must have high gain, low noise, and efficient power usage in order to guarantee precise monitoring and diagnosis. A common-source amplifier is used in the second stage of the suggested OTA to increase gain and bandwidth, while a differential amplifier is used in the first stage for strong common-mode rejection. An integrated compensating circuit enhances stability, while a biasing circuit guarantees appropriate operating conditions.In order to achieve an optimal trade-off between power efficiency, gain bandwidth (GBW), common-mode rejection ratio (CMRR), and phase margin, the circuit is developed and simulated using the Cadence Virtuoso IC design environment with a 180 nm CMOS technology. The findings show that the suggested amplifier is appropriate for biomedical signal acquisition since it achieves a gain of 28 dB, and a phase margin of 60°.
EEG, OTA, GBW, biomedical, amplifier, Virtuoso.
Challenges and Solutions in Low-Power ASIC Design for Edge Computing Applications
On the tail side, edge computing has become the technological innovation of importance due to the increasing demand for real time data processing in which the proliferation of Internet of Things (IoT) devices is one of the main drives. As sophistication of these applications increases, never ever has there been a greater requirement for energy efficient hardware solutions. Thus, among the powerful technologies that came into existence as a result of the novel challenges that edge computing environment brings, ASICs have also emerged. In this article, we explore challenges faced in coming up with low power ASIC for edge computing applications followed with an overview of innovative solutions to tackle these problems.By processing data closer to the source in the edge, edge computing provides lower latency, lower bandwith usage and a much better privacy and reliability. This distributed approach gives new constraints, foremost of which are power consumption and thermal management. ASICs, inherently matchable to target applications, are one of the ways to further optimize performance and reduce energy usage. saying that in this landscape, we examine some of the important consideration in the low power ASIC design and how this is affecting the way edge computing hardware is changing.
ASIC Design; Edge Computing; Low-Power Design; Power Efficiency; Resource Optimization; System-on-Chip (SoC)
Smart Sensors Embedded Systems for Environmental Monitoring System Integration
Currently, in our modern world, environmental monitoring is a necessity for us to act to prevent the destruction of the highly unpredictable ecosystems to humans. As we try to understand and tame pollution, climate change and resource depletion, smart sensors embedded in embedded systems have become a viable tool for collection, analysis and interpretation of marine environmental data. This paper studies the interaction between sensors, environmental monitoring application with sensors and embedded systems, and inherent challenges and potential opportunities that come with the interaction.We have the capability of gathering real time data about our surroundings by combining of sensor technology and embedded systems. They make possible such valuable insights from air quality measurements and water pollution detection to inform policy makers' decision making, and to help shape environmental policies. We will go in depth of this topic to discuss the components which consist of these systems, the type of sensors in use and the embedded system process and interpretation of the collected data.This article will analyse how the integration of these technologies could be applied to sensor embedded systems and how their technical aspects could be resolved, with real world examples and how they can help with current environmental issues. An understanding of what these systems can, or cannot, do can give us an understanding of their potential and how we can leverage the power that they are able to provide to build more environmentally aware societies.
Embedded Systems; Environmental Monitoring; IoT Integration; Smart Sensors; System Integration
Verification and Testing Techniques for Reliable System on Chip Solutions
Verification and Testing Techniques for Reliable System on Chip (SoC) Solutions is a class of research article that investigates the difficulties and advances in making certain that present day SoC outlines are dependable and accessible. With SoCs integrating complex components such as processors, memory and peripheral interface into a single chip, it becomes increasingly important to have efficient verification and testing methodologies. Simulation based verification, formal verification and emulation are some of the kinds of various form of verification that this article describes, along with various things it does to point out design flaw so that they can be identified early in the development process. Furthermore, testing strategies including scan based testing, built-in self test (BIST) and multi-level testing techniques, are also addressed for detecting faults and to achieve the eventual long term reliability of the SoC solutions. The paper examines emerging trends, including machine learning assisted verification, that holds potential to improve the efficiency of classic verification techniques. The article ultimately offers a comprehensive summary of strategies applicable for achieving robust and reliable SoC designs in a rapidly growing number of potential contaminates in the electronic landscape.
Built-in Self-Test (BIST); Emulation; Formal Verification; Reliability; Scan-based Testing; System on Chip (SoC)
Sustainable VLSI Design: Green Electronics for Energy Conscious Systems
Years have passed by and we have gone into an age of technology where electronic devices are being integrated in our daily lives. Smartphones to smart homes, these gadgets traverse the globe and have revolutionized the way we interact with each other as well as work and move in our lives. However, there comes a very large environmental cost to that boom. Because of the growing of electronic devices, energy consumption and electronic waste is a problem that we have no more to be without dealing with with something you cannot get rid of.In view of an atmosphere full of issues in a crowd, the very large scale integration (VLSI) design is moved towards green produce. This shift is not a by product of a trend but a necessity as electronics industry finally realises its environmental impact. The state of the art is research and development of the sustainable VLSI design — the energy efficient and environmental friendly electronic systems.Finally, in this article, the world of sustainable VLSI design is explored as it studies a specific aspect of green electronics and its role in shaping the path of energy conscious systems. We will take a look at the state of the art advancements and improvements, the challenges and possible solutions to the aforementioned dilemma of figuring out the correct balance of the advancement of this very fast moving industry and environmental stewardship.
Energy Conscious Systems; Information and Communication Technology; Electronic Waste Crisis; Green Electronics; VLSI, DVFS
SoC Solutions for Automotive Electronics and Safety Systems for Revolutionizing Vehicle Technology
Today, we are seeing an electronic and safety system driven era of profound change in the automotive industry. The System on Chip (SoC) is really focused on this revolution; it’s a powerful integrated Circuit (IC) that’s able to put several components in a single chip. Yet the latest-generation sophisticated SoCs are transforming how vehicles operate, communicate and protect their vehicle occupants, and more. The movement of cutting edge SoC solutions to automotive applications is reviewed, and evaluated in terms of its influence on vehicle performance, connectivity and safety.But with vehicles becoming more connected and autonomous – electronic systems are needing to be more powerful, efficient and secure. Modern vehicles have a variety of computational requirements that automotive manufacturers and suppliers are attempting to meet in order to achieve robust security, and automotive manufacturers and suppliers are racing to develop innovative SoC solutions that can accommodate these computational requirements. From advanced driver assistance systems (ADAS), to infotainment and control, automotive electronics are becoming the basis of such SoCs.As with all the latest trends of automotive SoC design and the challenges a developer has to go through in the market, this is a comprehensive study. Additionally, we will complete further discussion about the importance of cybersecurity for cybersecurity in these complex systems and cyber standards which define the conditions for the formation of these systems. To the world of automotive SoC technology, and how this is evolving to reach for the skies.
Automotive Electronics; Safety Systems; System on Chip (SoC); Vehicle Technology; Wireless Communication
Fabrication of Micro and Nano Electro Mechanical Systems Technology for Next Generation Sensors
The so called advanced sensing capability results from the common extensions of microelectromechanical systems (MEMS), nanoelectromechanical systems (NEMS) and very large scale integration (VLSI) technologies. This integration is paving the way for next generation sensors which are smaller, smarter and more powerful compared to their previous versions. So, in the coming time, we will see how all these technologies, when brought together, are becoming a sort of a industry that is disrupting various industries, and at the same time opening new avenues for innovation.This sensor technology breakthrough is a MEMS/NEMS based VLSI fusion technology. By combining the small size and precision of MEMS/NEMS together with the process power and functionality of a CMOS VLSI circuit, engineers and researchers design sensors that detect their environment and with very high sensitivity and accuracy. This is not incremental improvement; this is a paradigm shift, and it is making not just the sensing and data collection in this one domain, but many others.In this article as we go ahead we have a look to some fundamental principles of MEMS/NEMS technology and how VLSI helps to brings synergy in the MEMS/NEMS technology and the wide variety of anticipated application from MEMS/NEMS technology. They have profound and pervasive impact from healthcare to environmental monitoring, from automotive systems to consumer electronics.
MEMS/NEMS Technology; Microfabrication Techniques; Nanoimprint Lithography; Deep Reactive Ion Etching; Atomic Layer Deposition; Wafer-Level Packaging
Advancing Scientific Discovery: A High Performance Computing Architectures for AI and Machine Learning
In this time, when HPC and AI are converging, we are witnessing the era of combining HPC with AI, i.e. data, which will bring to bear new scientific discovery and innovation at unimagined speed. Computing approaches used in the past have been unable to keep up with growing datasets and increasingly sophisticated problems in research. With the combination of HPC systems and the power of analytic AI and machine learning, previously almost unsolvable problems are being tackled in areas such as climate, drug discovery, materials science, and many other. This paper presents how these cutting edge HPC architectures and technologies can support these breakthroughs, describes the challenges of delivering AI on HPC systems and what can be done about it and provides a strategy for organizations seeking to maximize the value of these powerful tools.
AI Optimization; High-Performance Computing (HPC); Machine Learning Algorithms; Parallel Processing; Scientific Simulations