Journal of Integrated VLSI, Embedded and Computing Technologies
Aim: The Journal of Integrated VLSI, Embedded and Computing Technologies (JIVCT),ISSN - 3049-1312 published by the Society for Communication and Computer Technologies (SCCTS), aims to be a leading international platform for disseminating high-quality, peer-reviewed research and review articles in the fields of VLSI (Very Large Scale Integration), embedded systems, and computing technologies. The journal's mission is to advance knowledge, foster innovation, and facilitate practical applications in these interconnected domains, promoting collaboration among researchers, engineers, and practitioners worldwide. Scope: The Journal of Integrated VLSI, Embedded and Computing Technologies (JIVCT), published by the Society for Communication and Computer Technologies (SCCTS), focuses on publishing high-quality, peer-reviewed articles in the following areas: VLSI Design and Architecture: Digital and analog design, FPGA, ASIC, low-power and high-performance circuits, CAD tools. Emerging VLSI Technologies: Nanotechnology, quantum VLSI, MEMS/NEMS, 3D ICs, photonic systems. Embedded Systems: Hardware-software co-design, real-time operating systems, IoT, energy-efficient systems. Computing Technologies: High-performance computing, parallel and distributed systems, cloud and edge computing, AI hardware. System Integration and Testing: SoC and SiP solutions, hardware-software integration, verification, reliability, thermal management. Interdisciplinary Applications: Biomedical systems, automotive electronics, cyber-physical systems, smart sensors, sustainable technologies. Key Features: High-Quality Content: Rigorous peer-review process. Open Access: Freely accessible to a global audience. Interdisciplinary Focus: Encourages integration across various fields. Innovative Research: Highlights novel methodologies and cutting-edge technologies. JIVCT aims to advance knowledge and foster innovation in VLSI, embedded systems, and computing technologies, contributing to advancements in both academia and industry Frequency of publication - It has Three issue per year Language - English Subject - Engineering Year of Starting - 2024 format of publication - Online Only ISSN - 3049-1312
Society for Communication and Computer Technologies
High-Performance Network-on-Chip Architecture with Congestion-Aware Adaptive Routing for Heterogeneous Multi-Core VLSI Systems
Due to the high-speed integration of heterogeneous processing elements in modern multi-core VLSI systems, increment in complexity of communication on chip has resulted in acute scalability limits and dynamic congestion in traditional Network-on-Chip (NoC) designs. Deterministic routing schemes although simple and simple to implement cannot scale to non-uniform and bursty traffic patterns that occur with heterogeneous workloads leading to high latency and early network congestion. In order to overcome these shortcomings, this paper presents a high- performance Network-on-Chip architecture with a lightweight congestion-sensitive adaptive routing scheme. This router is proposed to monitor dynamically the occupancy of buffers and the use of links to calculate an actual index of congestion in order to select the paths intelligently without any deadlock. It is designed to make use of optimal hardware overhead and to be able to scale to mesh-based heterogeneous multi-core platforms. Cycle-accurate simulation was done on 4x4 and 8x8 mesh topology with uniform traffic, hotspot traffic, and transpose traffic. Experimental outcomes prove up to 28 percent decrease in typical packet internship and 22 percent raise in saturation throughput and 17 percent increase in energy effectiveness than the traditional XY and partly adaptable routing plans. Hardware synthesis with the help of 45 nm CMOS standard-cell library proves that the proposed congestion-awareness logic imposes less than 6% area overhead with insignificant effects about the critical path delay. These findings confirm the usefulness of the proposed architecture in heterogeneous VLSI systems of high scalability and high performance.
VLSI Architecture; On-Chip Interconnect; Mesh Topology; Latency Optimization; Throughput Enhancement; Energy-Efficient Design; Router Microarchitecture.
Hardware–Software Co-Design Framework for Secure and Scalable IoT Embedded Systems
A fast increase in the number of Internet of Things (IoT) embedded systems has accelerated the necessity to have secure, efficient, and scalable computing systems that can execute within stringent resource limits. Traditional all software based security systems are characterised by high latency and power consumption and hardware based only solutions are inflexible and not very scalable. In a bid to overcome these problems, this paper suggests a secure hardware -software (HW-SW) co-design architecture of scalable lightweight embedded IoT systems which combines lightweight cryptographic acceleration and intelligent task partitioning. The proposed architecture is a combination of secure processing core, Hardware-accelerated lightweight encryption engine, secure boot and key management module and a security-sensitive scheduling module are implemented to offer optimised performance and high protection. Authenticated encryption based on Ascon and ECC-based key exchange are included to provide high levels of security at a small computational cost. The methodology is based on a multi-objective hardware-software partitioning approach to ensure the balance between the energy consumption concerns, latency concerns, and security concerns. The scheme is realised and tested on an embedded platform based on FPGA, where experimental results indicate a high improvement over the software-only implementations, such as less energy/encryption run, shorter execution time, and more resistance to timing and side-channel attacks. Scalability analysis also affirms consistence in throughput with predictable power expansion as the IoT node density increases. The findings prove that the design of the suggested co-design methodology delivers a secure-by-design architecture that is applicable to battery-operated and massive IoT deployments.
Hardware–Software Co-Design; IoT Security; Lightweight Cryptography; Embedded Systems; FPGA Acceleration; Secure Boot; Energy Efficiency; Side-Channel Resistance.
J. Btia, Md. Kolba, Barek F. Fatem, Md. Abbas
Thermal-Aware Floorplanning and Power Optimization Techniques for 3D Integrated SoC Architectures
Three-dimensional (3D) integrated System-on-Chip (SoC) architectures have been proposed, as a more attractive interest to address scaling problems of traditional planar plans to achieve other goals of increasing integration density, decreasing interconnect delay, and enhancing bandwidth. Nonetheless, vertical stacking is an extremely adverse thermal characteristic since it is associated with increased power density and reduced regions of heat dissipation, creating the severe thermal hotspots that deteriorate performance, boost leakage power, and enhance reduced long-term reliability. To meet these challenges, there is a need to have a single streamline optimization platform that would collectively address the thermal behaviour and power consumption at the early design phases. A multi-objective thermal-aware floor planning mechanism in 3D integrated SoCs is suggested in this work and involves consideration of power optimization mechanisms into the placement process. The proposed framework uses multi-objective optimization algorithm to reduce peak temperature, the overall power consumption, length of wire, and thermal resistance at the same time. Hotspot based compact thermal modelling method is included so that the layer wise temperature estimation is done correctly at every optimization stage. Also, dynamic voltage and frequency scaling (DVFS) and leakage-based power modelling is added to minimise further the thermal stress and power consumption. Experiments on standard benchmark circuit board stacks on multi-layer 3D stacks have shown considerable improvements as compared to traditional thermal-blind floor planning algorithms with up to 18-25 percent peak temperature reduction, 12-20 percent overall power savings and observable improvement in reliability metrics like mean time to failure (MTTF). Its findings can be used to verify that scaled co-optimization of power management and floor planning offers a reliable and scalable solution to the next-generation high-density 3D SoC architectures. The paper develops a global thermal power co-design architecture that enhances secure energy efficient and thermal resilient 3D integration solutions.
Hotspot Thermal Modeling; Dynamic Voltage and Frequency Scaling (DVFS); Through-Silicon Vias (TSVs); Thermal Hotspot Mitigation; Reliability-Aware Design.
Energy-Efficient FPGA Accelerator Architecture for Real-Time Convolutional Neural Network Inference
The option of real-time Convolutional Neural Network (CNN) inference has become a critical condition within the edge computing application, such as autonomous navigation, medical diagnosis, industrial automation, and intelligent surveillance system. Nevertheless, it is not an easy task to implement deep CNN models on resource-limited system environments because of the high computational complexity, large memory bandwidth usage, and tight limitations on power consumption. Field-Programmable Gate Arrays (FPGAs) have a bright future characterised by performance, flexibility, and energy efficiency, but current FPGA-based accelerators are also limited with regards to data reuse, fixed precision computation and suboptimal memory hierarchies. The current paper introduces a new energy-saving FPGA accelerator architecture, which is aimed at real-time CNN inference. It was proposed that the theoretically designed tiled dataflow interface (using adaptive tiling) enables modifications in quantization-aware computation and dynamic scaling between mixed precision in order to minimize switching activity in digital signal processing (DSP) utilization. There is a hierarchy of on-chip memory, including the use of double buffering, to reduce expensive off-chip accesses to the DRAM, and a power-conscience scheduling system which dynamically varies the degree of parallelism and clock frequency at any given level of workload intensity. The architecture is capable of working in INT4, INT8 and FP16 modes of operation so that an accurate-energy balance can be tuned. Experimental analysis with real numbers on typical CNN models has shown a strong enhancement in throughput / per watt and reduction in latency over traditional fixed precision FPGA accelerators, with only a small amount of accuracy losses. Its findings validate that to capitalize on scalable, high-performance, and energy efficient CNN inference in the future edge AI systems, coordinated optimization of calculation, memory movement and precision adaptation is crucial.
FPGA, CNN accelerator, energy efficiency, real-time inference, hardware acceleration, edge AI, quantization, systolic array
Design and Implementation of a Low-Power RISC-V Based SoC with Hardware Acceleration for Edge AI Applications
The examples of Edge Artificial Intelligence (AI) applications include Smart Surveillance, Wearable health, sensors in industry internet of things, and autonomous drones which have high performance harsh requirements in terms of power, area, latency, and cost. The older approach to microcontrollers is ineffective at delivering the processing capability of a contemporary deep neural network, and does not address the energy and cost limits of edge deployments usually as well as a state of the art System-on-Chip (SoC). In the proposed paper, the proposed design, implementation, and high-level examination of a low-power RISC-V based SoC with user programmable hardware accelerator to edge AI inference will be presented. The architecture suggested has a low power-saving RV32IMC RISC-V core together with closely coupled 8 x 8 MAC systolic neural accelerator, a banked on-the-chip SRAM memory hierarchy and a multi-domain power management device providing dynamic voltage and frequency scaling (DVFS). To reduce the off-chip memory access and maximise the data reuse, a memory organisation with weight-stationary dataflow plan is deployed with a double-buffered memory organisation. The SoC has been designed in System Verilog, and has been developed in a 28 nm low-power CMOS technology and created on an FPGA prototype using realistic workloads of CIFAR-10 CNN, Keyword Spotting and MobileNet-Tiny networks. The experiment findings point to a maximum speed of performance increase and energy per inference reduce of up to 8.7x and 6.3x respectively in execution over the software base RISC-V platform, and will peak at power just under 400 mW. The architecture can provide scalability, configurability and open standards compatibility, and can provide a low cost and energy efficient next-generation edge AI system.
RISC-V, Edge AI, Low Power SoC, Hardware Acceleration, Neural Network Accelerator, IoT, TinyML, Embedded Systems, Energy-Efficient Computing
Hardware Watermarking and Obfuscation Techniques for IP Protection in SoC Design Flows
The distributed semiconductor supply chain through globalisation of semiconductor design and outsourced fabrication has increased the risks of intellectual property (IP), unlicensed overproduction and reverse engineering in the distributed System-on-Chip (SoC) supply chains. With the growing investment of a third-party block IP blocks and heterogeneous block components in modern SoC platforms, safeguarding design properties in the entire RTL-to-GDSII implementation cycle has become a crucial issue. In this paper, a single, security aware design system, consisting of both proactive hardware obfuscation and reactive hardware watermarking in a typical, Electronic Design Automation (EDA) setting, is proposed. An RTL-level logic locking SAT resilience lock is implemented to create key-dependent functionality and output corruption in the maximum number of conditions with invalid keys. This is followed by inserting a 64-bit constraint-based digital watermark during physical synthesis and routing in order to be used in verification of post-fabrication ownership but without interference to actual functionality. This architecture has been measured to the ISCAS85 benchmark circuits and an AES-128 cryptography core being run on a 45 nm technology node. Experimental evidence shows that the average corruption of its output caused by an incorrect key is near to 50% Hamming Distance and the Power, Performance, and Area (PPA) overhead do not exceed 5%. Further security audit substantiates that sat protocol-based tests become more resistant and that it is resistant to watermark removal through resynthesis and optimization. The layered protection technique suggested has provided scalable and low overhead protection of IP protection in current SoC design flows, including the provision of both functional secrecy, as well as legal traceability.
SoC Security, Hardware Obfuscation, Logic Locking, IP Watermarking, SAT Attack Resilience, VLSI Design, Hardware IP Protection.
Benchmarking and Performance Evaluation of Chiplet-Based Architectures for Sustainable Heterogeneous Computing
With the semiconductor business on the verge of hitting its physical extreme of monolithic scaling and the economic constraint of the reticle limit, the chiplet-based systems that have become a core solution to high-performance systems. The move to modular silicon however presents intricate multi-dimensional trade-offs in terms of power delivery, area of silicon and interconnect latency. The paper is a benchmarking and performance analysis of chiplet-based computers, in this case with specific focus on sustainable heterogeneous computing environment. The main idea is to test the viability of disaggregated dies to decrease the environmental and economic impact of VLSI manufacturing. Using a strong simulation-based framework as a combination of Gem5 and McPAT to analyze efficiency of Die-to-Die (D2D) interconnect protocols, including Universal Chiplet Interconnect Express (UCIe), in comparison to the traditional monolithic benchmarks. To measure hardware lifecycle sustainability, we propose a new Yield-Adjusted Energy-Delay-Area Product (Y-EDAP) to compare new hardware products with those that have been previously developed. The experimental data illustrate that integrating chiplets with an interface impairs the ability to achieve latency by a marginal ratio of 5% (interface overhead), whereas it enables a 30% increase in manufacturing yield and an 18% decrease in the total system power with optimal use of heterogeneous nodes (e.g. mapping of I/O to mature nodes). These results demonstrate that modularity is a promising direction of the Green VLSI. This paper gives an initial roadmap and a standardised bench marking process to the design of the next generation of more environment friendly, modular heterogeneous systems.
Chiplet-based Architecture, Heterogeneous Computing, VLSI, Sustainable Computing, UCIe, Energy-Delay-Area Product (EDAP), Die-to-Die (D2D) Interconnects.
Reconfigurable Neuromorphic VLSI Processor for On-Chip Real-Time Sensor Analytics
On-chip analytics with extremely low-latency and energy-efficiency are required in the burgeoning area of intelligent sensor networks in healthcare, industrial automation and smart infrastructure. According to conventional processor architectures ( CPU, GPU, fixed-function accelerator) memory bottlenecks and high switching activity make them unable to satisfy hard constraints in real-time and power usage. In this piece of work, a reconfigurable neuromorphic VLSI processor is introduced with specific purpose of on-chip real time sensor analytics in edge environments. The proposed architecture affects an event-driven spiking neural core computation with a dynamically reconfigurable interconnect fabric and distributed on-chip memory subsystem that makes it possible to map adaptively to a heterogeneous workload using sensor streams. A design philosophy that focuses on hardware devices, less movement of data, small-scale storage of synapses, and part-time execution on its mode of operation connected with enhanced scalability and energy proportionality. The processor is an implementation of a CMOS VLSI design flow, and a reduction was more than twice in inference latency and energy consumption of the processor compared to a baseline using neuromorphic and FPGA technology, yet the processor remains responsive to multiple sensor modalities and in real time. The independent confirmation of experimental validation is done through use of biomedical and environmental sensor data sets to ensure stable throughput during dynamic workloads. The presented architecture provides a scalable and energy-conscious base of proposed next-generation embedded neuromorphic systems, providing them with practical implementation possibilities in wearable healthcare systems, independent IoT systems used in industries, and self-driving sensory nodes.
Reconfigurable VLSI Architecture, Neuromorphic Processor, Spiking Neural Networks, Real-Time Sensor Analytics, Edge AI Hardware, Low-Power Embedded Systems
Adaptive Voltage/Frequency Scaling in RISC-V SoC Platforms for Energy-Harvesting IoT Networks
IoT nodes based on energy harvesting have extremely fluctuating and intermittent power levels, rendering the traditional dynamic voltage and frequency scaling (DVFS) techniques to long-term and reliable computation unsustainable. Convincing DVFS-based systems are mainly workload-based systems, and cannot take this into consideration as it would result in an unstable state, failure of tasks or collapse of an energy buffer when used in harvesting-powered systems. The present paper proposes an adaptive voltage/frequency scaling system in harvesting mechanisms of RISC-V system-on-chip (SoC) platform to operate the IoT autonomously without consuming energy. The architecture proposed closely integrates the power management unit, runtime energy monitoring and multi-level voltage frequency control to specify dynamically the matching between the need in computation and potentially available harvested energy. In comparison to fixed frequency or traditional DVFS strategies, the innovative strategy provides real-time scaling with respect to the storage buffer conditioning and variations in input power, and thus allows the service against the intermittent supply of power. An evaluation of hardware-realistic more specifically includes representative workloads in sensing and processing and communication taking place under different harvesting profiles. The results of the experiments show that they reach up to 3540 percent reduction in average energy per task and the rate of task completion is greatly increased in comparison to the traditional DVFS methods. The temporal behaviour analysis also validates constant capacitor voltage regulation and adjustive switching of frequency in transitory events of energy. The proposed system offers a scalable and architecture level implementation of long-life self-powered IoT nodes based on programmable RISC-V systems, and is a feasible bridge to energy-neutral embedded computing.
RISC-V System-on-Chip (SoC); Adaptive Voltage and Frequency Scaling (DVFS); Energy-Harvesting IoT; Low-Power Embedded Systems; Power Management Unit (PMU); Energy-Neutral Computing
Thermal-Aware 3D TSV-Enabled NoC Topologies for High-Throughput SoC Accelerators
Network-on-Chip (NoC) architectures in three-dimensional (3D) Technology using TSV have become a solution of high bandwidth and integration capability to address the needs of high-throughput System-on-Chip (SoC) accelerators. Vertical stacking however means a large amount of power density and thermal coupling resulting in intensive hotspots and poor reliability. The presented work proposes a thermal-conscious topology optimization of 3D NoCs using a Multi-Objective Genetic Algorithm (MOGA) to optimize and reduce the latency along with peaked temperature and maximize the network throughput with TSV and power constraints. The developed approach combined compact thermal modelling into the evolutionary search procedure and allowed simultaneous optimization of the horizontal connexions, vertical TSV location and routing design. Another strategy that can be used to overcome the localised overheating during runtime is the use of a thermal-aware adaptive routing strategy. Extensive simulations prove that the optimized topologies lead to significant cutting of peak temperature and thermal gradient and also to better saturation throughput than the traditional 3D mesh architectures. The findings define a scalable and thermally efficient design process of next-generation high-performance SoC accelerators with high standards of operating under demanding power and reliability requirements.
Multi-Objective Genetic Algorithm (MOGA), System-on-Chip (SoC) Accelerators, Thermal Modeling, Hotspot Mitigation, High-Throughput Architectures, Evolutionary Optimization.
Kagaba J. Bosco, S. M Pavalam, L.J. Mpamije
Secure Multi-Domain VLSI Architecture with Hardware-Enforced Trusted Execution for Edge AI Devices
The use of Artificial Intelligence (AI) in the edge in rapid proliferation is the prime cause of enormous security vulnerabilities since such devices are likely to be deployed in physically accessible location that are highly vulnerable to side-channel and memory injection attacks. Custom software Trusted Execution Environments (TEEs) can sometimes be prohibitively costly in terms of computational overhead and latency (TEE), and cannot be implemented on power-limited IoT hardware. The suggested paper presents an innovative design of Secure Multi-Domain VLSI which is aimed at offering hardware-enforced isolation of Edge AI workloads. The architecture has a domain physical gate-level separation of the Public, AI-Inference, and Secure-Key domains, such that sensitive model weights and biometric data are disconnected with the compromised system components. The design combines low-power Security Primitives and one Physically Unclonable Function (PUF) to generate unique keys to a device and also a high-throughput AES-GCM cryptographic engine to perform real-time data integrity. It was designed and synthesized in Verilog HDL and a then-state of the art [e.g. 28nm/45nm] CMOS technology node. As indicated in the results of the experiments, the proposed hardware-enforced TEE can implement high throughput inference at a Total Power Consumption of [X] mW or at most a [X] % of the overhead versus non-secure baseline architectures. The study offers a scalable topology of the Security-by-Design in next-generation Edge AI chip, to offer an adequate protection on a chip-silicon level and at the same time meet the high power-usage demands of battery-powered machines.
VLSI Architecture, Edge AI, Hardware Security, Trusted Execution Environment (TEE), Security Primitives, Low-Power Design, Multi-Domain Isolation.
AI-Driven Design Space Exploration Framework for Low-Power FPGA-Based Heterogeneous Computing
This has been enabled by the growing complexity of heterogeneous computing architectures which concurrently combine CPUs and Field-Programmable Gate Arrays (FPGAs) to produce a huge and non-linear design space which is difficult to optimise manually. The conventional Electronic Design Automation (EDA) software tends to fail to balance between power-intensive needs and rigorous power constraints on edges and devices in mobile contexts. This paper will suggest an AI-based Design Space Exploration (DSE) platform that is specifically focused on low-power systems based on FPGA. The framework is based on a Bayesian Optimization (BO) engine that finds its way through the vast configuration space (high-dimensional) of loop tiling, resource allocation, and clock frequency, through the application of a Gaussian Process surrogate model. The optimization goal is aimed at minimising the Power-Delay Product (PDP) that is to make the hardware configurations found after the discovery to provide the best compensation between energy consumption and latency. Experimental findings with classic signal processing and deep learning objectives prove the idea that the suggested framework finds Pareto-optimal designs much faster than customary heuristic-based strategies. In particular, the framework attains as large as 35 percent reduction in PDP alongside reduction in total exploration time by 5 times the random search methods. The suggested solution is a fully scalable automated, energy efficient hardware-software co-design solution to modern embedded systems.
Design Space Exploration (DSE), Bayesian Optimization, FPGA, Low-Power Design, Heterogeneous Computing, Power-Delay Product (PDP), VLSI.
On-Chip Co-Processing Architectures for Concurrent Neuroelectrical and Hemodynamic Signal Analysis
The multimodal brain monitoring systems are progressively combining function of neuroelectrical signals, including electroencephalography (EEG), with hemodynamic signals, including functional near-infrared spectroscopy (fNIRS), to provide both the time-varying and metabolic definition of neural activity. Most current multimodal platforms are based on either off-chip computation or sequential signal processing pipelines, with the result that these platforms exhibit higher latency, power consumption, and do not work well in embedded and wearable applications. In this paper, an on-chip co-processing architecture will be described, designed to provide the capability to analyse both neuroelectrical and hemodynamic signals on the same embedded platform. The design proposed uses processing pipelines that are modality specific and work in parallel with the help of shared memory resource and synchronisation control logic to guarantee time alignment between modalities. Certain design decisions of hardware-based nature such as pipelined data processing, fixed-point calculation, and selective resource utilization are used to accomplish real-time functionality with low area and energy cost. An FPGA-based prototype was used to test the architecture and give it a feasibility evaluation. Experimental evidence indicates that there is an important decrease on end-to-end processing delay in relation to a sequential multimodal baseline, processing efficiency and energy per processed sample is also enhanced. These findings confirm the usefulness of on-chip parallel processing of multimodal neuro-monitoring loads. The suggested architecture offers scalable and energy-efficient real-time embedded brain monitoring and is an ideal solution to the next generation wearable neurotechnology and edge-based brain -computer interface systems.
On-chip processing, co-processing architecture, neuroelectrical signals, hemodynamic signals, multimodal biosignals, embedded systems, VLSI design
Embedded and Cloud Computing Integration for Smart Mobile Learning Applications Using Deep Reinforcement Learning
Smart mobile learning applications are becoming increasingly dependent on embedded devices which run with harsh limitations with regards to computation power, energy, and network variability. Although cloud computing is capable of providing scalable processing, storage capacities, the integration of embedded platforms to cloud infrastructure is still a big problem especially when it comes to use in resource and intensive and latency-sensitive learning applications. In this paper, the author proposes a smart embedded-cloud computing system of smart mobile learning applications relying on Deep Reinforcement Learning (DRL). This proposed solution defines the computation offloading problem and resource allocation issue as a sequential decision-making problem, according to which the DRL agent is a dynamic, in charge of deciding whether the learning tasks need to be performed locally on the embedded system or offloaded through edge servers or cloud servers. State space is a combination of device status, network status and task properties and the reward mechanism serves to manage the combination of execution latency, energy use and quality of service. Numerous experiments performed in a simulated mobile learning setting prove that the suggested DRL-based mechanism is more favourable, compared to traditional local execution, offloading to the cloud, and heuristic-based approaches, in terms of lower latency and energy consumption. The findings demonstrate the scalability and flexibility of DRA on dynamic mobile systems, so that the suggested model is a prospective indicator to the future-generation smart mobile learning systems combining embedded and cloud computing technologies.
Embedded systems; Deep reinforcement learning; Cloud–edge computing; Smart mobile learning; Computation offloading; Energy efficiency
Embedded AI Framework for Low-Latency Sentiment Analysis in Smart Content Curation Systems
The fast spread of digital content on multiple networks has caused the growth of the need of real time sentiment-informed analytics to improve user involvement and content delivery techniques. Convincing cloud-based AI Natural language processing (NLP) solutions, as powerful as they are, typically have a disadvantage in latency, bandwidth consumption and data privacy, in bandwidth-sensitive and low-latency settings. To overcome such issues, the framework of a new embedded artificial intelligence (AI) is provided in this paper to handle low-latency sentiment analysis in intelligent content curation systems. The suggested framework uses quantized deep learning networks that are particularly trained to run on resource-constrained edge computing platforms, i.e., the NVIDIA Jetson Nano and the Raspberry Pi 5. The use of a blend of hardware-aware pruning, 8-bit quantization, and mixed-precision training methods by the framework leads to a large scale of reductions in model complexity, power consumption without leading to predictive accuracy decrease. As experimentally shown, the optimised model has a high classification of 92 percent on a benchmark sentiment dataset and a reduction inference latency of less than 150 milliseconds, which is much lower than the limit of the real-time processing. In addition to that, power consumption is also minimised by 34 percent against baseline full-precision models, which underscores appropriateness of the strategy to embedded application with energy-saving. The system architecture integrates an effective data acquisition system and light weight text preprocessing platform and a real time inference system, which allows the smooth integration into intelligent media applications. This paper creates a base of the forthcoming embedded NLP systems, those able to work autonomously and effectively in semi-autonomic settings. It also highlights the possibility of using affordable hardware to do more intricate AI work and, in general, expand accessibility and scalability to real-life applications. These findings make this framework a practical option towards real-time sentiment analysis in intelligent communication infrastructure, personalised recommendation systems, as well as adaptive media content moderation in mobile and embedded systems.
Embedded AI, edge computing, deep learning optimization, low-latency inference, quantization, smart content systems
Embedded Machine Learning Framework for Real-Time Prediction of User Information Needs in Intelligent Systems
Embedded computing combined with machine learning has offered new opportunities of intelligent and context-aware systems able to make real-time decisions at the network edge. The paper presents a lightweight embedded machine learning system that can be used to make predictions on the information required by users dynamically in smart information retrieval scenarios. The suggested architecture incorporates enhanced neural designs into a Raspberry Pi 5-based edge device, making it be locally assertive to a cloud connexion. The system consists of a predictive core that is a compressed and quantised neural network, which has been trained with anonymised data of user interaction and search behaviour. The systematic optimization to 93 % prediction accuracy, 200 ms mean inference latency, and under 5 W power consumption allows real-time user intent prediction to be successfully run on the resource constrained hardware, which offers a basis to privacy preserving, low latency intelligent systems. It proves that it is practically feasible to introduce adaptive learning directly into edge devices, opening the way to the next generation of cognitive interfaces in which seamless interaction between perceptions, reasoning and individual user support is built into practical application.
Embedded systems, machine learning, edge computing, real-time analytics, neural inference, information retrieval, intelligent systems.
Embedded System Architectures for Passive IoT Device Monitoring
In this paper, a new embedded system architecture that is used to passively monitor and classify Internet of Things (IoT) devices behavior on the edge layer is introduced. The study will help fulfil the requirement of real time and non-invasive analytics in distributed smart settings where bandwidth, power, and computational resources are constrained. Visions of the proposed design The design is a unified co-design of the hardware and software based on an ARM Cortex-A processor and a reconfigurable FPGA-based packet capture engine. The high-speed data acquisition and timestamping is performed by the FPGA logic, whereas lightweight behavioral analytics and classification is performed by the ARM core. Observing metadata (passively) of communication allows profiling devices continuously without disrupting network protocols or causing extra latency. Results of experiments carried out on several embedded IoT testbeds show that it has an average detection latency of less than 3 ms and overall power consumption of only 2.8 W with continuous operation. Comparative measurements show higher adaptability and more precise measurement compared to the static and monitored baselines, and this proves that the suggested architecture is viable when it comes to edge-oriented behavioral monitoring. The results indicate that passive embedded architectures may contribute immensely to improving IoT visibility and trust assurance and still remain scalable and energy efficient in scale and large, heterogeneous deployments.
Embedded systems, IoT monitoring, FPGA, passive data capture, edge analytics, low-power design.
Hardware Acceleration of SSL/TLS Handshake Operations Using Embedded Cryptographic Engines
The handshake of the SSL/TLS in the times of ubiquitous connectivity and services based on data is a basic but computationally expensive part of safe communication. In this paper, a hardware-assisted variant of the SSL/TLS handshake accelerator is proposed and implemented in embedded and edge devices, with cryptographic operation optimization by use of modular cryptographic engines, implemented in FPGA. Its architecture can use RSA, ECC and AES-GCM algorithms and can easily integrate with tight embedded spaces. With the proposed system, the handshake completion time is improved 3.2-fold and the CPU usage has been reduced by 45 % in comparison to the traditional software-only systems due to the offloading of the compute-intensive encryption and decryption operations to a custom hardware module. The modular structure of the accelerator enables flexibility to work on any edge computing and IoT environment. Through experimental validation, real-time encryption offloading is feasible and that it enhances throughput by a large margin and latency is minimized to support secure IoT and web applications. In this study, the research paper highlights the possibility and practicality of cryptographic acceleration using a hardware-based approach as a foundation of next-generation low-latency secure communications models.
SSL/TLS accelerator, FPGA, embedded systems, cryptographic engine, handshake optimization, hardware offloading, latency reduction
Ultra-Low-Power VLSI-Enabled Embedded Systems for Neural Prosthetics: Toward Scalable and Real-Time Brain–Machine Interfaces
BMIs and neural prosthetics bring a world-revolutionizing promise in terms of defeating sensory and motor impairments in patients with neurological deficiencies. The current systems have severe drawbacks usually in the aspects of energy efficiency, effective interfacing with hardwares, and real-time capability, which renders them inappropriate in several wearable or implantable applications over a long period. The given paper suggests an ultra-low-power embedded architecture based on VLSI that has been especially tailored to overcome such limitations and facilitates elastic resource-constrained neural signal processing in real-time. The main aim of this study is to develop the compact, energy-efficient system-on-chip (SoC) platform which will consist of neural signal acquisition, spikes-based preprocessing, and embedded classification consumption of minimum power. The system is equipped with subthreshold analog front-end, hardware-efficient spike detectors, and a lightweight, embedded neural decoder combined with a dynamic power management unit, to reduce the energy requirements according to the demand of the workload. Simulation and FPGA-based prototype show that the system is capable of processing up to 64 channel of neural traffic at a rate exceeding 300 000 channels/second with average power-consumption below 120 micro-watts/ channel and a total processing-latency of 2.8 milliseconds. A comparative study shows major reduction in the amount of power consumption (~70%) compared to existing designs, without killing the signal fidelity or the decoder accuracy. This shows the functionality of the offered architecture and makes it appropriate to be implemented in next-gen neural prosthetic systems.In summary, the candidate VLSI-based embedded system offers a good way of creating ultra-low-power, real-time brain machine interfacing that can perhaps be used in an implantable biomedical device, adaptive neuro prosthesis, and closed loop neural control machine.
VLSI Architecture; Neural Prosthetics; Ultra-Low-Power Embedded Systems; Brain–Machine Interface; Real-Time Signal Processing; Subthreshold Circuits; Dynamic Power Management
Thermal-Aware Floorplanning and Optimization Framework for High-Performance Heterogeneous SoC Architectures in Edge-AI and Embedded Systems
The extreme growth of edge-AI and embedded systems has made it necessary to incorporate a range of dissimilar computing assets, such as CPUs, GPUs, NPUs, and memory blocks, into the same system-on-chip (SoC). The trend towards this kind of architecture ushers in extreme thermal management issues that affect reliability, performance and power efficiency. In this paper, a floor planning and optimization algorithm that is thermal conscious is proposed especially in high-performance heterogeneous SoC architecture. The potential framework has low peak temperature, reduces the thermal gradient, has more reliability of the entire system in that it is a combination of early stage thermal modelling, power density conscious placement algorithm, and dynamic thermal challenge approval. With simulation of real-world edge-AI workloads, up to 28 per cent fewer thermal hotspots and a 17 per cent better thermal uniformity were measured compared to commonly used floorplanning approaches. This paper is pioneering towards scalable thermal-driven design behaviors of embedded AI SoCs in future generation.
Thermal-aware floorplanning, Heterogeneous SoC, edge computing, AI accelerators, thermal modeling, floorplanning optimization, thermal hotspots, reliability, embedded systems, chiplet integration.
Carbon Nanotube FET-Enabled VLSI Architecture for Energy-Efficient Deep Learning Accelerators in Edge AI Systems
The growing need to apply edge artificial intelligence (AI), including technologies like live image recognition, self-driving cars and healthcare logistics, requires both energy-saving and high throughput hardware solutions. Conventional power-hungry CMOS-based accelerators are significantly affected by power, scaling, and thermal constraints, which encourages the development of exploratory approaches to new device technologies. The proposed VLSI architecture in this study is a Carbon Nanotube Field-Effect Transistors (CNTFETs) based deep learning accelerator, due to its outstanding electrical characteristics, such as ultra-high carrier mobility, extremely low leakage current, and great scalability. The aim is to design and prove the effectiveness of a convolutional neural network (CNN)-optimised CNTFET-optimised architecture to fit resource-constrained edge computing conditions. As energy consumption is a concern in the proposed system it uses quantization at arithmetic operators, memory-efficient dataflow, and power-gates on memory banks. The 7 layer CNN was implemented and simulated at both architecture and CNTFET device-level behaviors at 7-layer with Verilog (architecture level) and HSPICE (device level for CNTFET devices). The findings illustrate a 53 percent better energy usage and 41 percent less silicon extent than corresponding CMOS-based plans with little performance reduction. The results demonstrate the promise of CNTFET-based designs and architectures as potential future energy-efficient edge artificial intelligence hardware, in the emerging neuromorphic computing and deep learning fields.
Carbon Nanotube FET (CNTFET), VLSI Architecture, Deep Learning Accelerator, Edge AI Systems, Energy Efficiency, Quantized Neural Networks, Hardware Accelerator, Low-Power Design
Bio-Inspired Computing Architectures for Energy-Efficient Biomedical Signal Processing on Chip
Real-time biomedical signal processing has used a lot of energy-efficient applications, and with the increasing number of wearable, implantable, and portable healthcare instruments, the necessity will increase. The traditional von Neumann-based architectures provide high flexibility but with memory bottleneck and power consumption they are inapplicable in continuous monitoring anomalies in resource-constrained systems. In that regard, a new solution can be considered in bio-inspired computing architectures that reproduce the general features of the parallel, event-based, and low-power human brain. In this paper we present a neuromorphic computing architecture of the biomedical signal processing on-chip by spiking neural networks (SNNs) and analog-digital mixed-signal integrations. The architecture consists of an analog front-end consuming very low power to perform real-time acquisition of biosignals and coding of the spikes, and a digital SNN core to perform the sparse and asynchronous processing. The system was designed and simulated using a 65nm CMOS technology that makes it very energy efficient and latency efficient. In particular, it can realize up to 65 percent of energy savings per inference count and up to 40 percent low-latency processing over traditional biomedical processors using DSPs. It is tested with benchmark biosignal data such as ECG (MIT-BIH), EEG (Bonn university), and EMG (Ninapro) with use cases such as arrhythmia detection, epileptic seizure prediction, and gesture recognition that can be utilized in the prosthesis control. They include on-chip learning and high noise resistance of the spike-based representation and adaptive SNN classification, which makes the overall architecture more reliable in the environment where it would be used in practice in the biomedical setting. Due to the vast simulation efforts and comparison studies, the suggested structure shows a great possibility of providing a feasible architecture to the next-generation edge medical devices which requires ultra-low-power and real-time. The fact that it is reconfigurable and can be compatible with contemporary CMOS processes opens up the possibility of scalable applications of the same on a broad range of biomedical monitoring systems. The contribution of this work is the progress of neuromorphic engineering in the field of healthcare, where the biological efficiency and low power consumption found in nature are achieved and enter the device silicon domain in which personalized and continuous health monitoring can be delivered.
Bio-Inspired Computing, Neuromorphic Architecture, Spiking Neural Networks, Biomedical Signal Processing, Energy Efficiency, Edge AI, On-Chip Learning, Low-Power VLSI
Photonic VLSI Architectures for Ultra-Low-Latency High-Speed Signal Processing in 6G Edge Networks
The demand-driven by next-generation wireless networks has caused exponential growth in the number of applications that use data and the latency and throughput of data processing at an edge scale. Although traditional electronic Very-Large-Scale Integration (VLSI) designs have been well developed, they face fundamental challenges in terms of speed, bandwidth scalability, and energy efficiency skills, mainly in the polarizing performance demands of 6G edge environments. The paper offers the fresh idea of a photonic VLSI that incorporates the silicon photonics into a traditional VLSI structure to address these bottlenecks. It is proposed that the photonic-based interconnects, logic gates implemented in MachZehnder interferometer (MZI), and wavelength-division multiplexing (WDM) will be used in the proposed architecture to provide parallel high-bandwidth optical transmission of data and parallel computation of signals at ultra-fast speed. We describe a modular systems-based optics design flow and thoroughly simulate-based benchmark with the state of the art CMOS systems. Our findings prove that the architecture can operate up to 62 per cent faster in terms of latency, 5.2 times faster in terms of content delivery performance and corresponding low values of energy-per-bit, which proves the applicability of the approach in real-time signal processing in 6G edge networks. The overall learning point of the study is that photonic VLSI systems provide a scalable and energy-efficient avenue to address the excessive requirements of terabit-scale edge intelligence in subsequent 6G systems and establish the foundation of the future hybrid optoelectronic compute architecture.
Photonic VLSI, 6G Edge Networks, Ultra-Low-Latency, High-Speed Signal Processing, Silicon Photonics, Wavelength-Division Multiplexing (WDM), Optical Interconnects, Mach-Zehnder Interferometer (MZI), Edge Computing, Energy-Efficient Architectures, Optical Logic Gates, Electro-Optical Interfaces, Next-Generation VLSI, Terabit-Scale Data Processing, Real-Time Communication Systems
Design and Implementation of a Low-Power RISC-V Processor Core for Energy-Constrained Edge Devices
The paper entails the entire design and implementation of the energy efficient low power RISC-V processor core tailored specifically to energy limited edge computing platforms including wireless sensor networks, wearable biomedical device and intelligent IoT end points. As edge devices scale exponentially and demand efficient computing capability on-device, there is an urgent demand of programming frameworks which achieve custom and ultra-low power processing architectures to perform well within limited-energy constraints. The proposed processor core uses the open-source, modular design of the RISC-V instruction set architecture (ISA) to implement powerful low-power design techniques such as fine-grain clock-gating, power-gating and instruction-level parallelism to minimize dynamic and steady power usage. A five-stage pipeline based architecture that implements without some, or with some compressed instructions (RV32C), the RV32IM instruction set architecture has been implemented with System Verilog and has been prototyped and tested with a low-power FPGA development board. Application-specific benchmarks of real world IoT workloads have provided guidance on power-aware design decisions made in designing processors in IoT applications, including: sensor data processing, lightweight cryptography, and control logic calculations. Experimental analyses indicate that the suggested RISC-V essence attains an energy efficiency advantage of up to 43 percent over conventional RISC-V characters, with a similar computing performance and an insignificant area cost. Also, the design proves compatible with DVFS (Dynamic Voltage and Frequency Scaling) based methods which makes it even more appropriate to be used in energy-harvesting and battery-powered applications. All the processors are benchmarked with Vivado and ModelSim and power analysis with Vivado Power Estimator, and Synopsys PrimePower. The findings show that switching activity and leakage power has been reduced drastically in all test conditions. The work contributes to a feasible reference architecture that may be adopted by researchers and practitioners to design energy-autonomous embedded applications and systems, as well as the larger scope of scaling, and sustainability of edge intelligence in the next-generation ubiquitous computing systems. The next improvements will incorporate the use of ASIC implementation and collaboration with domain-specific accelerators of AI-powered tasks at the edge.
RISC-V, Low-Power Processor, Edge Computing, FPGA, IoT, Energy Efficiency, Clock Gating, Power Gating.
Hardware–Software Co-Design of RISC-V Embedded Systems for Ultra-Low-Power IoT Applications
This study intends to solve this challenge by suggesting a hardware-software co-design framework of ultra-low-power embedded systems using the RISC-V open-source architecture. The resulting system goes to extremes to maximize the hardware and software abstractions to satisfy problem-specific energy requirements, all the whilst maintaining efficiency of performance and scalability. The methodology offered consists of customization of instruction sets, hardware-based clock and power gating, and low-level software based technique inside compiler based optimization, sensor-sensitive task scheduling, and memory access improvement. An iterative profiling and tuning of a system can be done in a co-simulation system based on Verilator and Spike. A RISC-V core incurs environmental sensor workloads to validate the experimentally. Design All the co-designers showed an average power consumption of 38% (versus conventional ARM Cortex-M4 baseline), a 46 percent energy efficiency gain per task. Dynamic voltage and frequency scaling (DVFS) is another feature that can support flexibility of varying workloads. The conclusion of this research is that the hardware-software co-design applying RISC-V provides a suitable, extensible, open, and energy-efficient approach to the following-generation IoT devices. It is specially tailored to battery-powered and energy-gathering embedded platforms that can be later applied into the real deployment across smart environments, health, and industrial monitoring.
RISC-V, hardware–software co-design, ultra-low power, embedded systems, IoT, instruction set customization, power optimization, edge computing
3D IC Integration with Through-Silicon Vias for High-Density Computing Applications: Design and Thermal Considerations
The 3D integrated circuits (3D ICs) enabled by the technology of Through-Silicon via (TSV) has become a transformative technology to high density-computing application that overcomes the limitations of the traditional planar IC architecture, including the additional interconnect delay, interconnect bandwidth bottlenecks, and huge footprint. The ability of 3D ICs to allow vertical stacks of logic, memory, and compute layers allows greater performance, lower latency, and enormous area benefits. The application of many active layers, however, adds much design, temperature management complexity, especially relating to power density, thermal dissipation, and TSV-related stress. In reviewing this paper, you shall see that significant research has been conducted with regard to the design style, fabrication techniques as well as thermal factors linked to TSV-based 3D ICs. It describes such architectural strategies as floor planning, optimization of interconnects, and co-design of power delivery as well as advanced TSV fabrication processes such as deep reactive ion etching (DRIE) and copper electroplating. Thermal modeling in finite element analysis, simulation-based thermal hotspot evaluation with and without mitigation approaches such as thermal TSVs, and microfluidic cooling are given special attention. The example of a 3-tier AI accelerator stack is presented to illustrate how vertical integration affects performance metrics, showing a 35 percent decrease in latency and 50 percent area savings over 2D devices, as well as pointing at the potential threats of the thermal buildup due to the lack of effective cooling systems. Reliability and application in thermal, profiles and comparative performance analysis are presented to give a full picture of an 3D IC operation in a real-life workload. The paper also ends with the future research directions to be pursued such as TSV-free monolithic 3D ICs, AI-enabled thermal-aware design automation, and electronic-photonic integration. Its results form part of the effort to design thermally robust, performance-optimized 3D IC structures that can deliver on the performance requirements in the next-generation artificial intelligence, edge computing, and high-performance data centers.
3D IC, Through-Silicon via (TSV), Thermal Management, High-Density Computing, AI Accelerator, TSV Fabrication, Vertical Integration, Microfluidic Cooling, Power Delivery Network, Floor planning
Hybrid CMOS-Photonic VLSI Interconnects for Ultra-High Bandwidth and Energy-Proportional Chiplet Communication in 2.5D/3D Systems
The emerging intensive nature of data transfer in artificial intelligence (AI), cloud computing, and high-performance computing (HPC) increased the need to shift towards chiplet based systems. Nevertheless, conventional electrical connecting devices are fast being ill equipped to cater the bandwidth density, energy efficiency and thermal management factors in 2.5D/3D integrated system. With the introduction of CMOS-photonic VLSI systems-on-chip, ultra-high bandwidths and energy-proportional communication within and across chiplets are feasible in advanced packaging environments. This paper determines and proposes a hybrid CMOS-photonic VLSI interconnect architecture, which can achieve those ultra-high bandwidths and energy-proportional communication. To attain this goal, we suggest that a CMOS-compatible silicon photonic architecture be co-designed with electrical SerDes and interface circuitry so as to incorporate CMOS-compatible silicon photonic components, e.g., MachZehnder modulators (MZMs), ring modulators, and photodetectors. The energy management framework of workload-aware is also integrated to adjust power consumption of optical link dynamically according to the traffic demand. The proposed system is simulated as a multi domain system that involves CST Microwave Studio to design the electromagnetic part, COMSOL Multiphysics to model the thermal design and Synopsys OptSim to model the photonic link in the system. Simulation results show up to 10x bandwidth advantage and more than 60 percent energy-per-bit savings of a hybrid architecture over conventional copper based interconnects. Moreover, due to optimized layout design using TSV, the thermal simulations indicate that the proper cooling of the device can be achieved under its peak workloads. In summary, the hybrid CMOS-photonic interconnection proposed is an energy efficient, scalable and thermally feasible communication systems used in chiplets in 2.5D/3D chip fabrication providing solution to the bandwidth and energy bottlenecks of layer-to-layer communication in heterogeneous computing chip systems.
Hybrid CMOS-Photonic Interconnects, 2.5D/3D Integration, Chiplet Communication, Silicon Photonics, Energy-Proportional Design, High-Bandwidth On-Chip Communication, Thermal-Aware Packaging, VLSI System Architecture
Thermal-Aware System-on-Chip (SoC) Design for Real-Time Edge AI in Smart Healthcare Devices
This study aims at contributing to the thermal management issues that would arise when integrating AI features on a System-on-Chip (SoC) platform to perform real-time health monitoring on smart healthcare gadgets. With AI workloads getting more compute-intensive, particularly in wearables and implantable medical devices, the potential thermal limitations present an acute design concern in terms of performance and user safety. The paper suggest a thermal-aware SoC architecture, optimized towards edge-based applications of AI in healthcare. This method uses dynamic voltage and frequency scaling (DVFS), thermal-sensitive task scheduling and predictive throttling algorithms to use thermal sensors and optimize core placement spatially. The system has been made in such a way that full inference will be available in real time and minimize hotspots. The offered system was tested in comparison with the benchmark healthcare AI models (ECG classification and fall detection on a simulated AI-SoC prototype). The results indicate potential peak temperature level decreasing by up to 18 percent, an average inference latency of 58 milliseconds, and the power management overhead of fewer than 6 percent, which make it suitable to be used in medical-grade conditions during continuous monitoring. To summarize, the study has yet presented a scalable, thermally optimized AI-SoC, optimized to support smart healthcare. These results form the foundation of a safer and more reliable edge AI devices that will encourage the long-term implementation of a real-time diagnostics in health-critical facilities.
Thermal-Aware SoC Design, Edge AI Computing, Smart Healthcare Devices, Dynamic Voltage and Frequency Scaling (DVFS), On-Chip Thermal Management, Neural Processing Units (NPUs), Low-Power Medical AI Hardware, Real-Time Inference, Wearable and Implantable Devices, AI-Driven Thermal Optimization.
Reliability Analysis and Hardware Fault Injection for Safety-Critical Embedded Applications
A safety-critical embedded system is central to all applications that cause serious effect in case of failure, such as human injury, financial impact, or disruption of the entire system. Such systems are widely used in the realms of automotive control (e.g., automatic braking), airline navigation, automation of industrial processes and life-support medical devices. Therefore, their reliability and fault-tolerance of operation are a top priority. The proposed work presents a detailed framework of reliability analysis coupled with hardware fault injection (HFI) methodology that brings the serious fault tolerance capabilities of real-world fault scenarios of embedded systems under testability. The suggested approach will unite formal reliability modeling, where such metrics like the failure rate, mean time between failures (MTBF), fault recovery rate (FRR), and the mean time to recovery (MTTR) will be used, and the hardware fault injection based on the experimental hardware application, both FPGA-based platform and microcontroller-based platform. Classes of faults that the study systematically addresses are stuck-at faults, transient faults and memory corruption faults through the processor registers, memory arrays and within I/O peripherals. Two of their benchmark applications: an autonomous braking controller and a ventilator feedback system are safety-critical and made subject to controlled fault injection campaigns. The experimental data in terms of fault recovery prove that the fault recovery ratio is very high 94.7%, the system lacks significant fractional time in the fully down mode, and fast recovery is centralized on possessing redundant architectural elements and error-correcting codes (ECC). In addition, the trade-offs between area/power overheads and fault coverage are analyzed in terms of normal and abnormal detection latencies. The paper does not only prove the efficiency of the suggested fault-tolerant mechanisms, but also identifies certain potential weaknesses in the design that may go unnoticed in the traditional scheme of simulation-based testing. The framework complies with steps of functional safety, including ISO 26262, and IEC 61508, in terms of confirming pre-certification validation and soundness profiling of embedded systems. In general, the research introduces an ingenious scalable hardware-verified methodology of improving the resiliency of safety-critical embedded systems, and furthermore, leads the way to future applications in embedded system design involving the exploitation of smart fault prediction and fault mitigation policies.
Safety-Critical Embedded Systems; Hardware Fault Injection (HFI); Reliability Analysis; Fault Tolerance; Redundant Design; ECC; Safety Standards; Fault Recovery Rate (FRR); FPGA-Based Injection; Real-Time Monitoring; ISO 26262; MTTR.
A Scalable Parallel Processing Architecture for Real-Time and Energy-Efficient Biomedical Signal Analysis in Edge-Enabled Health Monitoring Systems
The trend in wearable Biomedical devices that integrate continuous health monitoring capabilities has also necessitated the need to analyze the wide range of signals in real-time with energy-efficient analysis at the edge. High latency and the lack of scalability require new line-based processing architectures that are more appropriate to perform the real-time computation of electrocardiogram (ECG), electroencephalogram (EEG), and electromyogram (EMG) signals processing. This paper presents a scalable work detector which is tailored towards edge enabled health monitoring systems and which has the goal of parallel processor architecture. The architecture incorporates the modular pipeline architecture and a hardware/software co-design approach such that preprocessing, feature extraction, and classes can be done simultaneously. Versatile balancing of work load across the numerous processing elements promises optimal performance and utilization of energy. It is prototyped on an FPGA based platform with embedded ARM cores and custom accelerators, and it is demonstrated based on real data in the biomedical applications. Results of experimentation show a 65% depletion of the processing latency and 48% enhanced energy efficiency as compared to single-core systems. These results indicate that the proposed architecture can serve as an efficient and scalable architectural solution that can help to realize real-time biomedical signals analysis in future edge-AI healthcare equipment.
Real-Time Signal Processing, Biomedical Signal Analysis, Edge Computing, Scalable Parallel Architecture, Hardware/Software Co-Design, ECG, EEG, EMG, FPGA Implementation, Energy-Efficient Processing, Wearable Health Monitoring