Hardware–Software Co-Design Framework for Secure and Scalable IoT Embedded Systems

Abstract

A fast increase in the number of Internet of Things (IoT) embedded systems has accelerated the necessity to have secure, efficient, and scalable computing systems that can execute within stringent resource limits. Traditional all software based security systems are characterised by high latency and power consumption and hardware based only solutions are inflexible and not very scalable. In a bid to overcome these problems, this paper suggests a secure hardware -software (HW-SW) co-design architecture of scalable lightweight embedded IoT systems which combines lightweight cryptographic acceleration and intelligent task partitioning. The proposed architecture is a combination of secure processing core, Hardware-accelerated lightweight encryption engine, secure boot and key management module and a security-sensitive scheduling module are implemented to offer optimised performance and high protection. Authenticated encryption based on Ascon and ECC-based key exchange are included to provide high levels of security at a small computational cost. The methodology is based on a multi-objective hardware-software partitioning approach to ensure the balance between the energy consumption concerns, latency concerns, and security concerns. The scheme is realised and tested on an embedded platform based on FPGA, where experimental results indicate a high improvement over the software-only implementations, such as less energy/encryption run, shorter execution time, and more resistance to timing and side-channel attacks. Scalability analysis also affirms consistence in throughput with predictable power expansion as the IoT node density increases. The findings prove that the design of the suggested co-design methodology delivers a secure-by-design architecture that is applicable to battery-operated and massive IoT deployments.