Thermal-Aware Floorplanning and Power Optimization Techniques for 3D Integrated SoC Architectures

Abstract

Three-dimensional (3D) integrated System-on-Chip (SoC) architectures have been proposed, as a more attractive interest to address scaling problems of traditional planar plans to achieve other goals of increasing integration density, decreasing interconnect delay, and enhancing bandwidth. Nonetheless, vertical stacking is an extremely adverse thermal characteristic since it is associated with increased power density and reduced regions of heat dissipation, creating the severe thermal hotspots that deteriorate performance, boost leakage power, and enhance reduced long-term reliability. To meet these challenges, there is a need to have a single streamline optimization platform that would collectively address the thermal behaviour and power consumption at the early design phases. A multi-objective thermal-aware floor planning mechanism in 3D integrated SoCs is suggested in this work and involves consideration of power optimization mechanisms into the placement process. The proposed framework uses multi-objective optimization algorithm to reduce peak temperature, the overall power consumption, length of wire, and thermal resistance at the same time. Hotspot based compact thermal modelling method is included so that the layer wise temperature estimation is done correctly at every optimization stage. Also, dynamic voltage and frequency scaling (DVFS) and leakage-based power modelling is added to minimise further the thermal stress and power consumption. Experiments on standard benchmark circuit board stacks on multi-layer 3D stacks have shown considerable improvements as compared to traditional thermal-blind floor planning algorithms with up to 18-25 percent peak temperature reduction, 12-20 percent overall power savings and observable improvement in reliability metrics like mean time to failure (MTTF). Its findings can be used to verify that scaled co-optimization of power management and floor planning offers a reliable and scalable solution to the next-generation high-density 3D SoC architectures. The paper develops a global thermal power co-design architecture that enhances secure energy efficient and thermal resilient 3D integration solutions.