Design and Implementation of a Low-Power RISC-V Based SoC with Hardware Acceleration for Edge AI Applications

Abstract

The examples of Edge Artificial Intelligence (AI) applications include Smart Surveillance, Wearable health, sensors in industry internet of things, and autonomous drones which have high performance harsh requirements in terms of power, area, latency, and cost. The older approach to microcontrollers is ineffective at delivering the processing capability of a contemporary deep neural network, and does not address the energy and cost limits of edge deployments usually as well as a state of the art System-on-Chip (SoC). In the proposed paper, the proposed design, implementation, and high-level examination of a low-power RISC-V based SoC with user programmable hardware accelerator to edge AI inference will be presented. The architecture suggested has a low power-saving RV32IMC RISC-V core together with closely coupled 8 x 8 MAC systolic neural accelerator, a banked on-the-chip SRAM memory hierarchy and a multi-domain power management device providing dynamic voltage and frequency scaling (DVFS). To reduce the off-chip memory access and maximise the data reuse, a memory organisation with weight-stationary dataflow plan is deployed with a double-buffered memory organisation. The SoC has been designed in System Verilog, and has been developed in a 28 nm low-power CMOS technology and created on an FPGA prototype using realistic workloads of CIFAR-10 CNN, Keyword Spotting and MobileNet-Tiny networks. The experiment findings point to a maximum speed of performance increase and energy per inference reduce of up to 8.7x and 6.3x respectively in execution over the software base RISC-V platform, and will peak at power just under 400 mW. The architecture can provide scalability, configurability and open standards compatibility, and can provide a low cost and energy efficient next-generation edge AI system.