Hardware Watermarking and Obfuscation Techniques for IP Protection in SoC Design Flows

Abstract

The distributed semiconductor supply chain through globalisation of semiconductor design and outsourced fabrication has increased the risks of intellectual property (IP), unlicensed overproduction and reverse engineering in the distributed System-on-Chip (SoC) supply chains. With the growing investment of a third-party block IP blocks and heterogeneous block components in modern SoC platforms, safeguarding design properties in the entire RTL-to-GDSII implementation cycle has become a crucial issue. In this paper, a single, security aware design system, consisting of both proactive hardware obfuscation and reactive hardware watermarking in a typical, Electronic Design Automation (EDA) setting, is proposed. An RTL-level logic locking SAT resilience lock is implemented to create key-dependent functionality and output corruption in the maximum number of conditions with invalid keys. This is followed by inserting a 64-bit constraint-based digital watermark during physical synthesis and routing in order to be used in verification of post-fabrication ownership but without interference to actual functionality. This architecture has been measured to the ISCAS85 benchmark circuits and an AES-128 cryptography core being run on a 45 nm technology node. Experimental evidence shows that the average corruption of its output caused by an incorrect key is near to 50% Hamming Distance and the Power, Performance, and Area (PPA) overhead do not exceed 5%. Further security audit substantiates that sat protocol-based tests become more resistant and that it is resistant to watermark removal through resynthesis and optimization. The layered protection technique suggested has provided scalable and low overhead protection of IP protection in current SoC design flows, including the provision of both functional secrecy, as well as legal traceability.