Benchmarking and Performance Evaluation of Chiplet-Based Architectures for Sustainable Heterogeneous Computing

Abstract

With the semiconductor business on the verge of hitting its physical extreme of monolithic scaling and the economic constraint of the reticle limit, the chiplet-based systems that have become a core solution to high-performance systems. The move to modular silicon however presents intricate multi-dimensional trade-offs in terms of power delivery, area of silicon and interconnect latency. The paper is a benchmarking and performance analysis of chiplet-based computers, in this case with specific focus on sustainable heterogeneous computing environment. The main idea is to test the viability of disaggregated dies to decrease the environmental and economic impact of VLSI manufacturing. Using a strong simulation-based framework as a combination of Gem5 and McPAT to analyze efficiency of Die-to-Die (D2D) interconnect protocols, including Universal Chiplet Interconnect Express (UCIe), in comparison to the traditional monolithic benchmarks. To measure hardware lifecycle sustainability, we propose a new Yield-Adjusted Energy-Delay-Area Product (Y-EDAP) to compare new hardware products with those that have been previously developed. The experimental data illustrate that integrating chiplets with an interface impairs the ability to achieve latency by a marginal ratio of 5% (interface overhead), whereas it enables a 30% increase in manufacturing yield and an 18% decrease in the total system power with optimal use of heterogeneous nodes (e.g. mapping of I/O to mature nodes). These results demonstrate that modularity is a promising direction of the Green VLSI. This paper gives an initial roadmap and a standardised bench marking process to the design of the next generation of more environment friendly, modular heterogeneous systems.