Thermal-Aware 3D TSV-Enabled NoC Topologies for High-Throughput SoC Accelerators

Abstract

Network-on-Chip (NoC) architectures in three-dimensional (3D) Technology using TSV have become a solution of high bandwidth and integration capability to address the needs of high-throughput System-on-Chip (SoC) accelerators. Vertical stacking however means a large amount of power density and thermal coupling resulting in intensive hotspots and poor reliability. The presented work proposes a thermal-conscious topology optimization of 3D NoCs using a Multi-Objective Genetic Algorithm (MOGA) to optimize and reduce the latency along with peaked temperature and maximize the network throughput with TSV and power constraints. The developed approach combined compact thermal modelling into the evolutionary search procedure and allowed simultaneous optimization of the horizontal connexions, vertical TSV location and routing design. Another strategy that can be used to overcome the localised overheating during runtime is the use of a thermal-aware adaptive routing strategy. Extensive simulations prove that the optimized topologies lead to significant cutting of peak temperature and thermal gradient and also to better saturation throughput than the traditional 3D mesh architectures. The findings define a scalable and thermally efficient design process of next-generation high-performance SoC accelerators with high standards of operating under demanding power and reliability requirements.