AI-Driven Design Space Exploration Framework for Low-Power FPGA-Based Heterogeneous Computing

Abstract

This has been enabled by the growing complexity of heterogeneous computing architectures which concurrently combine CPUs and Field-Programmable Gate Arrays (FPGAs) to produce a huge and non-linear design space which is difficult to optimise manually. The conventional Electronic Design Automation (EDA) software tends to fail to balance between power-intensive needs and rigorous power constraints on edges and devices in mobile contexts. This paper will suggest an AI-based Design Space Exploration (DSE) platform that is specifically focused on low-power systems based on FPGA. The framework is based on a Bayesian Optimization (BO) engine that finds its way through the vast configuration space (high-dimensional) of loop tiling, resource allocation, and clock frequency, through the application of a Gaussian Process surrogate model. The optimization goal is aimed at minimising the Power-Delay Product (PDP) that is to make the hardware configurations found after the discovery to provide the best compensation between energy consumption and latency. Experimental findings with classic signal processing and deep learning objectives prove the idea that the suggested framework finds Pareto-optimal designs much faster than customary heuristic-based strategies. In particular, the framework attains as large as 35 percent reduction in PDP alongside reduction in total exploration time by 5 times the random search methods. The suggested solution is a fully scalable automated, energy efficient hardware-software co-design solution to modern embedded systems.