Embedded System Architectures for Passive IoT Device Monitoring

Abstract

In this paper, a new embedded system architecture that is used to passively monitor and classify Internet of Things (IoT) devices behavior on the edge layer is introduced. The study will help fulfil the requirement of real time and non-invasive analytics in distributed smart settings where bandwidth, power, and computational resources are constrained. Visions of the proposed design The design is a unified co-design of the hardware and software based on an ARM Cortex-A processor and a reconfigurable FPGA-based packet capture engine. The high-speed data acquisition and timestamping is performed by the FPGA logic, whereas lightweight behavioral analytics and classification is performed by the ARM core. Observing metadata (passively) of communication allows profiling devices continuously without disrupting network protocols or causing extra latency. Results of experiments carried out on several embedded IoT testbeds show that it has an average detection latency of less than 3 ms and overall power consumption of only 2.8 W with continuous operation. Comparative measurements show higher adaptability and more precise measurement compared to the static and monitored baselines, and this proves that the suggested architecture is viable when it comes to edge-oriented behavioral monitoring. The results indicate that passive embedded architectures may contribute immensely to improving IoT visibility and trust assurance and still remain scalable and energy efficient in scale and large, heterogeneous deployments.