Hardware Acceleration of SSL/TLS Handshake Operations Using Embedded Cryptographic Engines

Abstract

The handshake of the SSL/TLS in the times of ubiquitous connectivity and services based on data is a basic but computationally expensive part of safe communication. In this paper, a hardware-assisted variant of the SSL/TLS handshake accelerator is proposed and implemented in embedded and edge devices, with cryptographic operation optimization by use of modular cryptographic engines, implemented in FPGA. Its architecture can use RSA, ECC and AES-GCM algorithms and can easily integrate with tight embedded spaces. With the proposed system, the handshake completion time is improved 3.2-fold and the CPU usage has been reduced by 45 % in comparison to the traditional software-only systems due to the offloading of the compute-intensive encryption and decryption operations to a custom hardware module. The modular structure of the accelerator enables flexibility to work on any edge computing and IoT environment. Through experimental validation, real-time encryption offloading is feasible and that it enhances throughput by a large margin and latency is minimized to support secure IoT and web applications. In this study, the research paper highlights the possibility and practicality of cryptographic acceleration using a hardware-based approach as a foundation of next-generation low-latency secure communications models.