Hybrid CMOS-Photonic VLSI Interconnects for Ultra-High Bandwidth and Energy-Proportional Chiplet Communication in 2.5D/3D Systems
DOI:
https://doi.org/10.31838/JIVCT/02.03.10Keywords:
Hybrid CMOS-Photonic Interconnects, 2.5D/3D Integration, Chiplet Communication, Silicon Photonics, Energy-Proportional Design, High-Bandwidth On-Chip Communication, Thermal-Aware Packaging, VLSI System ArchitectureAbstract
The emerging intensive nature of data transfer in artificial intelligence (AI), cloud computing, and high-performance computing (HPC) increased the need to shift towards chiplet based systems. Nevertheless, conventional electrical connecting devices are fast being ill equipped to cater the bandwidth density, energy efficiency and thermal management factors in 2.5D/3D integrated system. With the introduction of CMOS-photonic VLSI systems-on-chip, ultra-high bandwidths and energy-proportional communication within and across chiplets are feasible in advanced packaging environments. This paper determines and proposes a hybrid CMOS-photonic VLSI interconnect architecture, which can achieve those ultra-high bandwidths and energy-proportional communication. To attain this goal, we suggest that a CMOS-compatible silicon photonic architecture be co-designed with electrical SerDes and interface circuitry so as to incorporate CMOS-compatible silicon photonic components, e.g., MachZehnder modulators (MZMs), ring modulators, and photodetectors. The energy management framework of workload-aware is also integrated to adjust power consumption of optical link dynamically according to the traffic demand. The proposed system is simulated as a multi domain system that involves CST Microwave Studio to design the electromagnetic part, COMSOL Multiphysics to model the thermal design and Synopsys OptSim to model the photonic link in the system. Simulation results show up to 10x bandwidth advantage and more than 60 percent energy-per-bit savings of a hybrid architecture over conventional copper based interconnects. Moreover, due to optimized layout design using TSV, the thermal simulations indicate that the proper cooling of the device can be achieved under its peak workloads. In summary, the hybrid CMOS-photonic interconnection proposed is an energy efficient, scalable and thermally feasible communication systems used in chiplets in 2.5D/3D chip fabrication providing solution to the bandwidth and energy bottlenecks of layer-to-layer communication in heterogeneous computing chip systems.
