Design and Implementation of a Reconfigurable ASIC Architecture for Low-Power Secure Communication in IoT Devices

Abstract

The goal of the paper is to introduce and describe low-power and secure reconfigurable ASIC architecture as a solution optimized to operate in resource-constrained Internet-of-Things (IoT) devices. The main aim would be to come up with a new hardware product which intertwines efficient use of energy, lightweight cryptographic processing and dynamic runtime scalability to fit the requirements of the next-generation IoT platforms. The suggested system incorporates a cryptographic engine which is centered on PRESENT cipher, configurable key-length (80/128 bit ), power-saving characteristics like clock gating and power gating. This was proved in 65nm CMOS technology and synthesized on Synopsys Design compiler, and its functional and timing verification was done with the Cadence post layout simulation tools. The architecture meets all the requirements, and experimental results show that the architecture can be used in a battery-powered and wearable IoT, as it has peak throughput of 45 Mbps, a total power consumption of less than 1.5 mW at 0.9 V. It also has minimal area and latency overhead to allow the architecture of enabling adequate runtime reconfiguration between encryption modes. Scalability Single-chip that solves the dilemma of low-power and data confidentiality in the IoT communication ecosystem: The proposed design proposes a scalable and efficient solution to Hardware security. It also provides an already successful base of further development with the inclusion of post-quantum cryptographic support and increased resistance to side-channels.