Challenges and Solutions in Low-Power ASIC Design for Edge Computing Applications
DOI:
https://doi.org/10.31838/JIVCT/02.03.02Keywords:
ASIC Design; Edge Computing; Low-Power Design; Power Efficiency; Resource Optimization; System-on-Chip (SoC)Abstract
On the tail side, edge computing has become the technological innovation of importance due to the increasing demand for real time data processing in which the proliferation of Internet of Things (IoT) devices is one of the main drives. As sophistication of these applications increases, never ever has there been a greater requirement for energy efficient hardware solutions. Thus, among the powerful technologies that came into existence as a result of the novel challenges that edge computing environment brings, ASICs have also emerged. In this article, we explore challenges faced in coming up with low power ASIC for edge computing applications followed with an overview of innovative solutions to tackle these problems.By processing data closer to the source in the edge, edge computing provides lower latency, lower bandwith usage and a much better privacy and reliability. This distributed approach gives new constraints, foremost of which are power consumption and thermal management. ASICs, inherently matchable to target applications, are one of the ways to further optimize performance and reduce energy usage. saying that in this landscape, we examine some of the important consideration in the low power ASIC design and how this is affecting the way edge computing hardware is changing.