Design and Implementation of a Low-Power RISC-V Processor Core for Energy-Constrained Edge Devices

Abstract

The paper entails the entire design and implementation of the energy efficient low power RISC-V processor core tailored specifically to energy limited edge computing platforms including wireless sensor networks, wearable biomedical device and intelligent IoT end points. As edge devices scale exponentially and demand efficient computing capability on-device, there is an urgent demand of programming frameworks which achieve custom and ultra-low power processing architectures to perform well within limited-energy constraints. The proposed processor core uses the open-source, modular design of the RISC-V instruction set architecture (ISA) to implement powerful low-power design techniques such as fine-grain clock-gating, power-gating and instruction-level parallelism to minimize dynamic and steady power usage. A five-stage pipeline based architecture that implements without some, or with some compressed instructions (RV32C), the RV32IM instruction set architecture has been implemented with System Verilog and has been prototyped and tested with a low-power FPGA development board. Application-specific benchmarks of real world IoT workloads have provided guidance on power-aware design decisions made in designing processors in IoT applications, including: sensor data processing, lightweight cryptography, and control logic calculations. Experimental analyses indicate that the suggested RISC-V essence attains an energy efficiency advantage of up to 43 percent over conventional RISC-V characters, with a similar computing performance and an insignificant area cost. Also, the design proves compatible with DVFS (Dynamic Voltage and Frequency Scaling) based methods which makes it even more appropriate to be used in energy-harvesting and battery-powered applications. All the processors are benchmarked with Vivado and ModelSim and power analysis with Vivado Power Estimator, and Synopsys PrimePower. The findings show that switching activity and leakage power has been reduced drastically in all test conditions. The work contributes to a feasible reference architecture that may be adopted by researchers and practitioners to design energy-autonomous embedded applications and systems, as well as the larger scope of scaling, and sustainability of edge intelligence in the next-generation ubiquitous computing systems. The next improvements will incorporate the use of ASIC implementation and collaboration with domain-specific accelerators of AI-powered tasks at the edge.