Novel Programming Models with High-Level Synthesis Optimizations for Adaptive Reconfigurable Accelerators
Keywords:
High-Level Synthesis (HLS), Reconfigurable Computing, Domain-Specific Accelerators, Hardware-Software Co-design, Adaptive Hardware, Programming Abstractions, Field-Programmable Gate Arrays (FPGA), Resource-Aware Optimization.Abstract
To close this crucial divide between the high-level software abstraction and the structural intricacy of specialised hardware, the present paper plans to develop a new programming model along with a set of High-Level Synthesis (HLS) optimizations that are specifically tailored to adaptive reconfigurable accelerators. Most HLS flows of the past are also effective in mapping workloads that are deterministic and limited to a set of predictable kernels to hardware, whereas they typically do not scale well to workloads that have specific characteristics that are now non-deterministic and time-varying in nature (or that have yet to be characterised at all). We will overcome this shortcoming by means of a domain specific programming interface which is an interface that lets developers explicitly define adaptive behaviours and data guided execution paths without necessarily having a background in low-level Register-Transfer level (RTL) design. We supplement this implementation-level high-level model with HLS transformation passes that involve resource-aware dynamic scheduling and speculative hardware generation that optimise the datapath to become flexible at runtime, instead of fixed and fixed-common pipeline execution. In order to test the performance of the proposed framework, we deployed the frame-work on an FPGA-based reconfigurable fabric with a set of customary industry-standard benchmarks. Our hardware-software co-design method is shown to reduce the design effort by a significant margin despite offering up to a 1.5x area -efficiency and 20 percent throughput improvement over the state-of-the-art baseline designs in the state-of-the-art HLS. Moreover, the framework ensures high clock rates through reduction of the overheads of the run time reconfiguration logic. With the programming model and the synthesis engine closely combined we allow the creation of a smooth, automatic way between high level, algorithm representations, and highly efficient adaptive realization on hardware. This is a scalable base to the next generation of the heterogeneous computing systems wherein the hardware will have to dynamically adapt with the changing computational needs.
