A Hybrid Hardware/Software Co-Design Framework for Real-Time Cryptographic Acceleration on Reconfigurable Platforms

Abstract

The requirements conflicting with the consistency and flexibility of the algorithmic libraries and the deterministic hardware speed are becoming a challenge to modern high-performance cryptographic systems. Although software-defined security provides quick flexibility to changing standards, it cannot usually satisfy strong timing, based on real-time embedded systems, game the stringent timing ensures of such systems as non-deterministic OS overhead and jitter based on cache. The present paper would suggest a powerful Hybrid Hardware/Software Co-Design Framework that would be tailored toward real-time cryptographic acceleration on a reconfigurable System-on-Chip (SoC) platform. We adopt a tactical functional division: the work in the control-intensive subsystem, e.g. key exchange protocol and session management, will be scheduled on a General Purpose Processor (GPP) and computationally lintelate data-plane primitives to a specialized Field Programmable Gate Array (FPGA) logic. In order to bridge these areas we propose a dedicated Direct Memory Access (DMA)-based communication layer with a zero-copy memory mapping technique. This architecture optimization is able to cut the amount of CPU usage by 40, which essentially solves the issue of communication bottleneck that is prevalent in hybrid systems. The model was designed and tested on a Xilinx Zynq-7000 SoC with AES-256 used as its main benchmark. Experimental evidence shows that there is a strong exceeding 12 times throughput improvement over software-only optimised baselines. More importantly, the system achieves deterministic times of response of less than a milliseconds and very low latency variance, which makes it suitable to hard real time applications. Our results find that the hybrid solution suggested here offers a scalable and agile end of edge computing solution, the one that balances high throughput but at the same time meets the high standards of predictability that industrial security and automotive security protocols entail.