Dynamic Hardware Adaptation for Multichannel Neurophysiological Feature Extraction

Abstract

The multichannel neurophysiological signal processing systems should have to meet strict and usually competing criteria connected with the latency, throughput and power performance along with adaptability. In real-world electroencephalography (EEG), electromyography (EMG), and electrocardiography (ECG) recording and acquisition, channel counts, quality of signals, and complexity of feature ideation are major challenges to pipeline software and hardware accelerators with fixed functionalities. These traditional methods do not possess the ability to be flexible so that they can easily meet dynamic workloads without compromising on real-time performance. This article has described a dynamically reconfigurable multichannel neurophysiological feature extraction hardware architecture based on an FPGA platform and intended to be used to facilitate adaptive and high-energy-efficiency real-time processing. The given architecture uses the capabilities of runtime partial reconfiguration to allocate computational resources in a dynamic manner due to the number of active channels, as well as the assigned task(s) and the task(s) to perform a specific feature extraction. It implements a single processing architecture to enable time-domain, frequency-domain and timefrequency feature extraction in the same reconfigurable platform. The feature extraction modules can be changed dynamically without disrupting the flow of operation of the system, hence dynamic capability to adapt to varying requirements of the signals and application. The implementation and evaluation of the architecture is done on the basis of a field-programmable gate array (FPGA) platform under realistic multichannel neurophysiological workloads. The experimental performance is better in terms of utilizing the available hardware resources and lowering energy consumption than the energy consumption of fixed FPGA-based designs, and maintains deterministic low-latency performance. These findings affirm that dynamic partial reconfiguration is a feasible idea to scalable and power efficient neurophysiological signal processing. The suggested architecture offers a versatile hardware base of future generation real-time brain-computer interfaces, wearable biomedical systems, and adaptive neuro-monitoring software.