Design of Ultra-Low-Power Photonic Interconnects for Next-Generation System-on-Chip Communication Architectures

Abstract

The paper is relevant to/concerned with the critical problem of interconnect energy efficiency enhancement in System-on-Chip (SoC) systems with the increasing load of artificial intelligence, edge, and high-performance applications. The current electrical interconnects are subject to physical and power scaling limits, making the key consideration in possible photonic interconnects one that can be considered in light of being low-energy and high-speed. New Designs For low power 3D pycnointerconnectthe design features, microring resonators, optical modulators, and waveguides made of silicon with low insertion loss and drive voltage. An electronic-photonic interface is developed, a hybrid electronic-photonic interface and could be used to bridge voltage domains with minimum dynamic energy overhead. The 7nm FinFET CMOS technology along with silicon photonics is used to implement the system. Simulation and testing show that energy-per-bit is less than 0.5 pJ/bit, data rates (>=20 Gbps) and an area overhead are low. Its interconnect has high thermal robustness, staying functional at +/- 20-degree C. The architecture is a response to the needs of SoC systems with a high-bandwidth and low-latency and power-constrained system architecture. It is more so appropriate to software scalable AI acceleration, chiplet designs, and heterogeneous multi-core systems. Directions are moving towards dynamic wavelength allocation, integration with machine learning workloads and transitioning to chip-scale prototyping to permit commercialization. It is the contribution of this work to make a scalable energy-efficient communication backbone of futuristic smart systems and continuous attempts towards energy-saving semiconductor technology innovations.