Design and Optimization of Energy-Efficient VLSI Architectures for Edge AI in Internet of Things (IoT) Applications

Abstract

The demand of the edge of the network in processing Artificial Intelligence (AI) in real time and in low power has more increased due to the rapid growth in the number of Internet of Things (IoT) devices that are being connected to the network. Traditional cloud-based AI systems are also plagued with high latency, power and bandwidth, which makes them not ideal in large-scale time-bound IoT applications. The current work develops an overall exploration of energy-efficient Very Large-Scale Integration (VLSI) architectures and optimization of architecture to fit Edge AI applications. The targeted approach combines low-power design techniques, such as, approximate computing, clock gating, quantization and dataflow-driven hardware acceleration, to minimize the power use without compromising accuracy of inference. The architecture uses parallel processing units, light neural network models, and near-memory computing to reduce overhead of transferring data. They are implemented on FPGA prototypes and on post-layout VLSI simulations in a 28 nm CMOS process, up to 42% in power savings, 28% in latency and 15% in throughput over accelerators with the baseline design. Such findings highlight the promise of dedicated VLSI architectures to feasibly provide long-term, scalable and intelligent computing at the edge to support next-generation IoT ecosystems.