[1]
Kagaba J. Bosco, S. M Pavalam, L.J. Mpamije, “Thermal-Aware 3D TSV-Enabled NoC Topologies for High-Throughput SoC Accelerators”, Journal of Integrated VLSI, Embedded and Computing Technologies, vol. 3, no. 2, pp. 14–24, Feb. 2026, Accessed: Mar. 05, 2026. [Online]. Available: https://ecejournals.in/index.php/JIVCT/article/view/508