A Scalable Reconfigurable Processor Architecture for Heterogeneous Edge Computing Applications

Authors

  • Ernst Uken Faculty of Engineering, University of Cape Town (UCT), South Africa Author
  • David Gichoya Department of computing and information technology, kenyatta university, Nairobi, Kenya Author

DOI:

https://doi.org/10.31838/RCC/03.02.05

Keywords:

Reconfigurable Computing, Edge Computing, Dynamic Partial Reconfiguration (DPR), Heterogeneous Processing, FPGA-based Architecture, Software-Hardware Co-Design, Processing Element (PE), Workload Classification, Low-Power Embedded Systems, Runtime Adaptability

Abstract

Edge computing has become a revolutionized paradigm to address the rising need of handling low-latency, high-throughput, and energy efficient local data computing. Nevertheless, heterogeneity and dynamic nature of edge workloads, which can consist of AI inference and multimedia processing as well as cryptographic operations and sensor fusion, are challenging traditional fixed-function processors. Such processors do not tend to possess the elasticity to support and run a variety and changing assignments effectively in the limited resources settings. In an attempt to resolve these constraints, this paper suggests a new Scalable Reconfigurable Processor Architecture (SRPA) that uses the dynamic capability of Field-Programmable Gate Arrays (FPGAs) in conjunction with the dynamic partial reconfiguration (DPR) and AI-based workload management. Its unique missionable Processing Elements (PEs) are modular and can adapt themselves (at runtime) to various types of computation: signal processing units, neural accelerators or encryption engines. A fine-grained hardware should be able to receive orchestration of fine-grained Reconfiguration Management Unit (RMU) driven by real-time input of a lightweight On-Chip Workload Classifier (OWC) that makes use of machine learning to detect and forecast task requirements. It allows the dynamic assigning of computational resources on demand with as little power consumption and throughput as possible. Architecture assessment is based on Xilinx Zynq UltraScale+ MPSoC platform over photo//fig-stcitionsa-ealslesimpedelobc Shadow toay blocks such as convolutional neural network inference, fast Fourier transform and public-key encryption workloads. It has been demonstrated that SRPA can reduce energy required by up to 65 percent and increase tasks adaptability by more than 4 times as compared to static FPGA and legacy CPU based designs. The design proposed will not only assist in increasing the flexibility of runtime and responsiveness of the system but also a scalable base of future heterogeneous edge platforms. The potential of the SRPA lies in its high potential of becoming a promising next-gen reconfigurable computing solution that supports alterability, performance, and efficiency requirements of the edge systems.

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Published

2025-09-17

Issue

Section

Articles

How to Cite

A Scalable Reconfigurable Processor Architecture for Heterogeneous Edge Computing Applications (Ernst Uken & David Gichoya , Trans.). (2025). SCCTS Transactions on Reconfigurable Computing , 3(2), 40-48. https://doi.org/10.31838/RCC/03.02.05