Scalable Reconfigurable Architectures for Quantum-Inspired Computing: Design, Challenges, and Opportunities

Abstract

This paper focuses on exploring the scalable reconfigurable hardware for quantum-inspired computing (QIC), a computing paradigm which simulates quantum properties on classical hardware to solve complex problems related to optimization, simulation and machine learning. This mainly aims at reducing the gap between the complexity of the computations required by QIC algorithms and the processing power of standard hardware through the use of reprogrammable systems like the Field Programmable Gate Arrays (FPGAs) or Coarse-Grained Reconfigurable Arrays (CGRAs). The subject of methodology is the architecture study, design-space exploration and determining the parameters which are thought to be critical such as parallelism, pipelining performance and hardware-software co-design co-integration. The principles of modularity, optimizing data locality and partial runtime reconfiguration are focused so that to increase the scalability and flexibilities. The issue of resource constraints, routing congestion, synchronization delay and energy efficiency is well addressed. Experimental findings show that the flexibility of reconfigurable logic leads to the utilization of the workloads of QIC, especially when working with iterative and matrix-related computing. The boost in performance is further enhanced by use of approximate computing, in-memory operations and dynamic reconfiguration techniques. The paper passes the conclusion that scalable reconfigurable architecture is an option to speed quantum-inspired algorithms and make practical usage in the area of edge computing, embedded computing, and high-performance computing. The opportunities in the future will be described in the paper such as combination of quantum and classical with hybrid integration and neuromorphic acceleration in order to improve the performance and scalability of the systems.