Dynamic Task Migration and Partial Reconfiguration in Heterogeneous FPGA Clusters for Adaptive Computation Offloading
DOI:
https://doi.org/10.31838/RCC/03.01.09Keywords:
Dynamic Task Migration, Partial Reconfiguration, Heterogeneous FPGA Clusters, Adaptive Computation Offloading, Runtime Reconfigurable Systems, Edge Computing AccelerationAbstract
The growing requirement of higher performance and energy efficient computing at the edge and cloud-edge has escalated the use of heterogeneous FPGA clusters. The distinct selling point of such platforms is their reconfigurability that best suits workloads that are dynamic and where latencies are an issue. This review entails an in-depth discussion of two important factors in the enablement of runtime flexibility of such systems: dynamic task migration, and partial reconfiguration (PR). Dynamic task migration enables migration of tasks across the processing units depending on requirements of the available resources, heat, or performances. At the same time, partial reconfiguration ensures that it is possible to modify, on the fly, hardware modules in the system without affecting overall system behavior. Composing these methods provides the opportunity to flexibly and in fine detail control the computation offloading approaches, making the use and allocation of resources more effective and efficient in terms of energy consumption. This paper summarizes the state of art in the area of task migrating policy, PR methodologies, runtime frameworks and design tools, as well as outlining the synergies and trade-offs. Moreover, there is a discussion on the real-world applications, such as edge AI inference, secure system reconfiguration, and adaptive multimedia processing to show some practical applications. Lastly, proved challenges in research and future work directions within the paper are the following: intelligent scheduling, PR-aware system architecture and multi-vendor FPGA ecosystem standardization. This review can be used as the basic point of reference by researchers and practitioners who need to develop adaptation and reconfiguration computing platforms with FPGA.