A Review of Software/Hardware Co-Design Strategies in Reconfigurable Systems for High-Performance Computing

Abstract

The current article allows to deeply review the software/hardware co-design (SW/HW co-design) solutions that are specific to reconfigurable systems in the sphere of high-performance computing (HPC). The rising power consumption, scalability and rigidity characteristics of a fixed-architecture platform are creating bottlenecks as compute requirements increase still further across a variety of modern applications, including scientific simulation, machine learning, and real time data analysis. Field-programmable gate arrays (FPGAs) and coarse-grained reconfigurable arrays (CGRAs) have emerged as a potential technology solution to achieve the desired customizability and parallelism in processing with a hardware and software optimizable platform. The given paper surveys the history of the development of SW/HW co-design methodologies and points out how it transformed, with its primary changing focus now on high-level synthesis (HLS), OpenCL-based programming, and AI-enabled design automation. Co-design frameworks, toolchains (e.g., Xilinx Vitis, Intel OpenCL SDK), and design models are critically analyzed, and a survey of optimization techniques, including loop pipelining, memory tiling and partial reconfiguration are given. The review classifies and contrasts current efforts in the areas of application as well as reporting increases in throughput, latency, power efficiency, resource usage. Case studies have shown that, co-designed FPGA systems can sometimes be energy efficient and power consuming compared to CPU and GPU based counterparts and hence appealing to edge-to-cloud HPC application. Nevertheless, problems like toolchain fragmentation, absence of standard abstractions, difficult verification, and ability to configure the system at runtime with little support continue to cause problems. Additional newer trends that are discussed in the paper include AI-assisted design space exploration, secure co-design, and where reconfigurable systems and cloud-edge federated computing meet. Finally, a sum-up of the current status-of-the-art of software / hardware co-design of reconfigurable HPC systems is given and it also becomes clear what research efforts must be done to having scalable, efficient and smart computing systems over a wide range of applications.