An Energy-Efficient FPGA-Based Architecture for Real-Time Edge AI Applications

Abstract

The proposed research offers the novel energy-efficient Field-Programmable Gate Arrays (FPGAs)-based architecture that is specifically designed to be energy efficient in the context of real-time Edge AI applications. The fast-growing distribution of smart edge devices in areas like smart surveillance, wearable health, and industrial IoT necessitates computing architectures, which entangle low-latency inference, high power-efficiency, and flexibility in limited environments. Conventional CPUs and GPUs usually cannot meet the demand because of power consumption and heart issues and insufficient flexibility to handle the changing workloads as required. In order to overcome these disparities the proposed system is based on a low power FPGA platform with highly optimized quantized neural network accelerator along with a simplified dataflow execution engine. The architecture facilitates 8-bit integer (INT8) quantized models and uses pipelined parallelism, on-chip memory reuse tactics as well as a hardware/software-co-design to reduce off-chip memory access and maximize its throughput. Moreover, dynamic voltage and frequency scaling (DVFS) and the clock gating techniques are incorporated in order to minimize the power consumption at idle phases or in a low load state. Patented hybrid inference model is employed, preprocessing, and other non-critical operations are offloaded to ARM Cortex cores, whereas compute-intensive layers are accelerated on the reconfigurable logic fabric. A wide range of experiments have been performed on the typical edge AI benchmarks, which encompass image classification on CIFAR-10 and ImageNet samples as well as object detection on VOC2007. Up to 3.2 times less power consumption and 2.5 times higher inference throughput have been shown by comparative analysis with Raspberry Pi 4B with Coral TPU and NVIDIA Jetson Nano. It is also designed to allow individual reconfiguration of the hardware at runtime to allow responsiveness to different workload pressures without a complete system redeployment. This FPGA-based architecture is compact in form, can be reused across different models and has extreme low power energy per inference (~51.6 mJ), delivering high performance and excellent energy efficiency in the application of real-time AI inference on the edge, elevating the industry standard reconfigurable computing design to embedded intelligent edge devices.