Neuromorphic Hardware Architectures for Event-Driven Signal Processing: Design, Optimization, and Applications in Low-Power Intelligent Systems - U. Tudevdagva; Wesam Ali (National Journal of Electrical Electronics and Automation Technologies, 2025)
Neuromorphic hardware architectures, based on the event-driven and massive parallel processing of the human brain, introduce a game-changing solution to energy-efficient signal processing in intelligent systems functioning at the edge. The paper gives a design and optimisation of a scalable event-driven neuromorphic hardware framework that is optimised to perform event-driven signal processing (EDSP) at low power. This architecture combines Address-Event Representation (AER) communication scheme, hierarchy of synaptic memory systems, asynchronous clusters of processing elements and adaptive spike coding to take advantage of the sparseness of real world sensory data. To reduce power consumption without adversely affecting accuracy, design optimisations such as dynamic voltage and frequency scaling (DVFS), clock gating, approximate computation and parallel event routing are utilised. The architecture was carried out and hosted on a Xilinx Zynq UltraScale+ FPGA device and proved via ASIC level simulation. Experiments involving benchmark datasets (N-MNIST for vision and TIDIGITS for audio, and an industrial vibration event dataset) have shown up to 35% energy per event and 42% processing latency reductions when compared to state-of-the-art neuromorphic processors, with classification accuracy above 95 percent achieved. Our proposal can perform in real-time with sub-10 187 Deployment in industry, predictive maintenance The proposed system exhibits, on average, less than 50 mW of power consumption and less than 50 mW of latency in an industrial predictive maintenance application. Based on these results the provided neuromorphic architecture becomes one of several plausible solutions to intelligent systems formulated at the edge with significant benefits to its robustness, low latency and ultra-low power processing capabilities within the edge computing domains including industrial Internet of Things, autonomous robots, wearable health devices and smart surveillance. At some point there will be an attempt to integrate it with a memristive synaptic array, and hardware-friendly learning algorithms to allow increased flexibility in actual implementation.