Mixed-Signal SoC for Ultra-Low-Noise Sensor Interfaces in Next-Generation Electronic Systems

Abstract

The paper proposes and demonstrates the implementation and experimental evaluation of a mixed-signal system-on-chip (SoC) to give optimal interface to the ultra-low-noise sensors of next-generation electronic systems. Designed with an industrial automation, IoT, and biomedical signal acquisition in mind, the proposed architecture integrates a chopper-stabilized analog front-end (AFE), high-resolution data acquisition, on-chip digital signal processing, yielding better noise performance and integration than other designs. Bucking the trend In 65 nm CMOS, SoC performance includes an input-referred noise of 95 nV\rms across a 0.1-10 kHz bandwidth, signal-to-noise ratio (SNR) of more than 96 dB, and power of less than 0.7 mW per channel. The interface has an extended reconfigurable sensor interface allowing a variety of sensor modalities (analog and digital) with a minimum of external circuitry. The proposed SoC will be over 20 percent more noise-resistant and 15 percent higher energy efficiency when compared with state-of-the-art solutions, which would allow noise-resistant high-sensitivity sensor data capture in resource-constrained applications.