A Low-Power CMOS RF Front-End Design for Next-Generation IoT Devices in Sub-GHz Bands

Abstract

With IoT rapidly advancing, there is a growing need for small, power-efficient, and cost-saving RF modules for gadgets working at 433 MHz, 868 MHz, and 915 MHz frequencies. Thanks to their ability to support long-distance communication, heavy signal penetration, and very little interference, they are often chosen for use in remote monitoring, smart metering, and factory sensor systems. In order to meet this goal, this work outlines how we designed and tested a RF front-end suitable for future IoT devices. With 180 nm CMOS fabrication, the proposed architecture uses a low-noise amplifier (LNA), a double-balanced mixer, a ring-based voltage-controlled oscillator (VCO), and a power amplifier (PA), all made to use less energy without sacrificing important aspects of performance. Employing techniques such as reusing current, degenerating the input source, and using adaptive biasing helps maintain a good trade-off between the noise figure, linearity, gain, and energy efficiency. Post-layout simulation shows that the front-end has a high gain of 20.6 dB, has an excellent noise figure of 2.3 dB, and delivers –12.5 dBm at its input third-order intercept point (IIP3), all while consuming only 2.8 mW of power with a 1.2 V supply. This study proved that the design meets the needs for high-efficiency and affordability in industrial IoT devices that use Sub-GHz spectrum.