An Energy-Efficient DSP Pipeline for Real-Time Audio and Image Processing in Battery-Constrained Embedded Systems

Abstract

Embedded systems that operate on batteries are becoming more involved with executing advanced tasks related to processing audio and image information within strict power limitations. To deal with this problem, this paper presents a new energy-conservative digital signal processing (DSP) pipeline to be implemented on battery-constrained platforms to support real-time multimedia inference. Its architecture relies upon the algorithmic approximations, data reuse optimization, and dynamic voltage-frequency scaling (DVFS) to reduce the degree of computational overhead to a significant degree. The pipeline contains a hybrid of a fixed-point arithmetic engine that is used to provide high-volume, low-power operation without affecting the fidelity of the signal. The described DSP pipeline isentedal and tested on a System-on-Chip (SoCostrained RISC-V-based fabricated in 65M cmos node. Experimental results on real-word data-sets show up to 42 per cent reduction in power envelope along with 33 per cent improvement in throughput per watt compared to the state-of-the-art embedded processors in use. It further advances the accuracy of classification and quality of images further under sub-50 mW power budgets. The findings make the proposed automatic pipeline a resilient and scalable approach in solving energy-constrained embedded systems that are deployed to perform Internet of Things (IoT), wearable computing, and autonomous sensing solutions. Future directions will involve the ability to further exploit CNN-DSP hybrid acceleration, not to mention adaptive task-aware pipeline reconfiguration.