Ultra-Low-Power DSP Architecture for Continuous Wake-Word Detection

Abstract

The concept of continuous wake-word detection enables devices to offer a smart speaker and wearable experience, as well as Internet-of-Things (IoT) gadgets, to always-on voice interfaces. Nevertheless, long-term acoustic monitoring with strongly limited energy economies is one of the largest problems of battery powered systems. This paper proposes a digital signal processing (DSP) architecture that is an ultra-low-power implementation with a particular focus on continuous wake-word detector in resource-constrained embedded systems. The above architecture incorporates a streaming fixed point based feature extraction pipeline, in place FFT computation, memory conscious circular buffering and multiplier sharing techniques as a way of minimising switching activity and memory access overhead. Learned convolutional neural networks (CNN) classifier on a mixed-precision arithmetic are applied to create a quantization-aware (quantization-aware) classifier, the detection accuracy and energy consumption of which can balance. Clock gating and dynamic control logic obtained on block level reduces more idle power when the trigger is not activated. Testing is done on the system by using the Google Speech Commands dataset on continuous inference. As the experimental results show, competitive accuracy in the use of the technique to detect in contrast to conventional microcontroller-based floating-point implementations, the system reduces footprint of the memory and energy utilized by one wake-word detection, showing significantly higher. The given design reaches real time performance with better power consumption, hence it is going to be applicable in always-on voice-triggered load in low-power edge devices. The architecture offers a scalable base to subsequent ASIC and FPGA executions understandable to be under sub-milliwatt.